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ST72C171
8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs (Software Programmable Gain Amplifiers), OP-AMP
PRODUCT PREVIEW
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Memories - 8K of single voltage Flash Program memory with read-out protection - In-Situ Programming (Remote ISP) Clock, Reset and Supply Management - Enhanced Reset System - Low voltage supervisor (LVD) with 3 programmable levels - Low consumption resonator or RC oscillators (internal or external) and by-pass for external clock source, with safe control capabilities - 3 Power Saving modes 22 I/O Ports - 22 multifunctional bidirectional I/O lines: - 16 interrupt inputs on 2 independent lines - 8 lines configurable as analog inputs - 20 alternate functions - EMI filtering 2 Timers and Watchdog - One 16-bit Timer with: 2 Input Captures, 2 Output Compares, external Clock input, PWM and Pulse Generator modes - One 8-bit Autoreload Timer (ART) with: 2 PWM output channels (internally connectable to the SPGA inputs), 1 Input Capture, external clock input - Configurable watchdog (WDG) 2 Communications Interfaces - Synchronous Serial Peripheral Interface (SPI) - Serial Communications Interface (SCI)
SO34
PSDIP32
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3 Analog peripherals - 2 Software Programmable Gain Operational Amplifiers (SPGAs) with rail-to-rail input and output, V DD independent (band gap) and programmable reference voltage (1/8 V DD resolution), Offset compensation, DAC & on/off switching capability - 1 rail-to-rail input and output Op-Amp - 8-bit A/D Converter with up to 11 channels (including 3 internal channels connected to the Op-Amp & SPGA outputs) Instruction Set - 8-bit data manipulation - 63 basic Instructions - 17 main addressing modes - 8 x 8 unsigned multiply instruction - True bit manipulation Development Tools - Full hardware/software development package
Device Summary
Features Flash - bytes RAM (stack) - bytes Peripherals ST72C171K2M 8K Single Voltage 256 (128) ST72C171K2B
2 SPGAs, 1 Op-Amp, 2 SPGAs, Watchdog, 3 Timers, SPI, SCI, ADC (11 chan.) Watchdog, 3 Timers, SPI, SCI, ADC (11 chan.) Operating Supply 3.2 V to 5.5 V CPU Frequency Up to 8 MHz (with up to 16 MHz oscillator) Temperature Range - 40C to + 85C Package SO34 PSDIP32
Rev. 1.4
October 2000
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
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Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 CLOCK, RESET AND SUPPLY REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 23 5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 OP-AMP MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.5 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.6 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.8 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.9 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 106 .. 8.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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9 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.13 OP-AMP MODULE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 147 11.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72C171 is a member of the ST7 family of Microcontrollers. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST72C171 features single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Under software control, the device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unFigure 1. ST72C171 Block Diagram signed multiplication and indirect addressing modes The device includes a low consumption and fast start on-chip oscillator, CPU, Flash program memory, RAM, 22 I/O lines and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs, Op-Amp module, synchronous SPI serial interface, asyncronous serial interface (SCI), Watchdog timer, a 16-bit Timer featuring external Clock Input, Pulse Generator capabilities, 2 Input Captures and 2 Output Compares, an 8-bit Timer featuring external Clock Input, Pulse Generator Capabilities (2 channels), Autoreload and Input Capture. The Op-Amp module adds on-chip analog features to the MCU, that usually require using external components.
OSCIN OSCOUT VDD VSS RESET
Internal MULTIOSC CLOCK + CLOCK FILTER POWER SUPPLY LVD
PORT A PWM/ART TIMER 16-BIT TIMER 8-BIT ADC PA[7:0]
CONTROL 8-BIT CORE
ADDRESS AND DATA BUS
OP-AMP
VDDA VSSA
ALU
OA3PIN* OA1OUT OA2OUT OA3OUT* PC[5:0]
PORT C SCI PORT B SPI PB[7:0]
8K FLASH MEMORY
256b-RAM
WATCHDOG
*only on 34-pin devices
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1.2 PIN DESCRIPTION Figure 2. 34-Pin SO Package Pinout
OA2OUT PWM1R / OA2PIN / PC1 OA2NIN / PC0 OA3PIN TDO / PB7 RDI / PB6 ISPDATA / MISO / PB5 MOSI / (HS) PB4 ISPCLK / SCK / (HS) PB3 SS / (HS) PB2 ARTCLK / (HS) PB1 EXTCLK / (HS) PB0 VDD VSS OSC2 OSC1 ISPSEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ei0 ei1
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
PC2 / OA1PIN / PWM0R PC3 / OA1NIN OA1OUT PC4 / MCO/ OA3NIN VDDA VSSA OA3OUT PC5/ PWM0 PA7 / AIN7 / PWM1 PA6 / AIN6 / ARTICP0 PA5 / AIN5 PA4 / AIN4 / OCMP1 PA3 / AIN3 / OCMP2 PA2 / AIN2 / ICAP1 PA1 / AIN1 / ICAP2 PA0 / AIN0 RESET
(HS) 20mA high sink capability
Figure 3. 32-Pin SDIP Package Pinout
OA2OUT PWM1R / OA2PIN / PC1 OA2NIN / PC0 TDO / PB7 RDI / PB6 ISPDATA / MISO / PB5 MOSI / (HS) PB4 ISPCLK / SCK/ (HS) PB3 SS / (HS) PB2 ARTCLK / (HS) PB1 EXTCLK / (HS) PB0 VDD VSS OSC2 OSC1 ISPSEL
1 2 3 4 5 6 7 8 9 10 11
32 31 30 29 28 27
PC2 / OA1PIN / PWM0R PC3 / OA1NIN OA1OUT PC4 / MCO VDDA VSSA PC5 / PWM0 PA7 / AIN7 / PWM1 PA6 / AIN6 /ARTICP0 PA5 / AIN5 PA4 / AIN4 / OCMP1 PA3 / AIN3 / OCMP2 PA2 / AIN2 / ICAP1 PA1 / AIN1 / ICAP2 PA0 / AIN0 RESET
ei1
26 25 24 23 22
ei0
12 13 14 15 16 21 20 19 18 17
(HS) 20mA high sink capability
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply In/Output level: C = CMOS 0.3VDD/0.7VDD, CR = CMOS Levels with resistive output (1K) A = Analog levels Output level: HS = high sink (on N-buffer only), Port configuration capabilities: - Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog - Output: OD = open drain, T = true open drain, PP = push-pull Note: the Reset configuration of each pin is shown in bold. Table 1. Device Pin Description
Pin n SDIP32 SO34 Pin Name Level Type Output Input Port Input float wpu ana int Output OD PP Main function (after reset) OA2 output X X ei1 ei1 ei1 ei1 ei1 ei1 ei1 ei1 X X X X X X X X X X X X X X X X X X X X X X Port C1 Port C0 Port B7 Port B6 Port B5 Port B4 Port B3 Port B2 Port B1 Port B0 OA2 noninverting input and/or ART PWM1 resistive output OA2 inverting input OA3 noninverting input C C C C C C C C HS HS HS HS HS X X X X X X X X SCI transmit SCI receive SPI data master in/slave out or In Situ Programming Data Input SPI data master out/slave in SPI Clock or In Situ Programming Clock Output SPI Slave Select (active low) ART External Clock Timer16 External Clock
Alternate function
1 1 OA2OUT PC1/OA2PIN/ 22 PWM1R 33 PC0/OA2NIN 4 OA3PIN
O I/O
A C C/CR X C X
I/O C/A I I/O I/O A
4 5 PB7/TDO 5 6 PB6/RDI
6 7 PB5/MISO/ISPDATA I/O 7 8 PB4/MOSI 8 9 PB3/SCK/ISPCLK 9 10 PB2/SS 10 11 PB1/ARTCLK 11 12 PB0/EXTCLK 12 13 VDD 13 14 VSS 14 15 OSC2 15 16 OSC1 16 17 ISPSEL 17 18 RESET 18 19 PA0/AIN0 19 20 PA1/AIN1/ICAP2 I I/O I/O I/O I/O I/O I/O I/O I/O S S
Digital Main Supply Voltage Digital ground voltage Resonator oscillator inverter output or capacitor input for RC oscillator External clock input or Resonator oscillator inverter input or resistor input for RC oscillator C C C C X X X ei0 ei0 X X X X X X X In Situ Programming Mode Select Must be tied to VSS in user mode External Reset Port A0 Port A1 ADC input 0 ADC input 1 orTimer16 input capture 2
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Type
Pin n SDIP32 SO34 Pin Name
Level Output Input
Port Input float wpu ana int Output OD PP
Main function (after reset) Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port C5 OA3 output Analog ground Analog supply
Alternate function
20 21 PA2/AIN2/ICAP1 21 22 PA3/AIN3/OCMP2 22 23 PA4 /AIN4/OCMP1 23 24 PA5/AIN5 24 25 PA6/AIN6/ARTICP0 25 26 PA7/AIN7/PWM1 26 27 PC5 / PWM0 - 28 OA3OUT 27 29 VSSA 28 30 VDDA 29 31 PC4/MCO/OA3NIN 30 32 OA1OUT 31 33 PC3/OA1NIN PC2/OA1PIN/ 32 34 PWM0R
I/O I/O I/O I/O I/O I/O I/O O
C C C C C C C A
X X X X X X X
ei0 ei0 ei0 ei0 ei0 ei0 X
X X X X X X
X X X X X X X
X X X X X X X
ADC input 2 or Timer16 input capture 1 ADC input 3 or Timer16 output compare 2 ADC input 4 or Timer16 output compare 1 ADC input 5 ADC input 6 or ART input capture ADC input 7 or ART PWM1 output ART PWM0 output
I/O O I/O C/A
C A C
X
X
X
X
Port C4 OA1 output
Main Clock Out or OA3 inverting input OA1 inverting input OA1 non-inverting input and/ or ART PWM0 resistive output
X
X X
X X
X X
Port C3 Port C2
I/O C/A C/CR X
Notes: 1. In the interrupt input column, "eix" defines the associated external interrupt vector. If the weak pull-up column (wpu) is associated with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see dedicated See "PIN DESCRIPTION" on page 5. for more details.
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1.3 MEMORY MAP 1.3.1 Introduction Figure 4. Program Memory Map
0000h
HW Registers (see Table 1.3.2)
007Fh 0080h
0080h
00FFh 0100h
Short Addressing RAM Zero page (128 Bytes)
256 bytes RAM Stack
017Fh 0180h
(128 Bytes)
Reserved
DFFFh E000h
017Fh
8 Kbytes FLASH
FFDFh FFE0h
Interrupt & Reset Vectors (see Table 4)
FFFFh
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1.3.2 Data Register Table 2. Hardware Register Memory Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh to 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h to 0030h 0031h 0032h 0033h 0034h0035h 0036h0037h 0038h0039h 003Ah003Bh 003Ch003Dh 003Eh003Fh 0040h TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 OA1CR OA2CR OA3CR OAIRR OAVRCR MISCR1 SPIDR SPICR SPISR WDGCR CRSR Block Name Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR Register name Data Register Data Direction Register Option Register Not Used Data Register Data Direction Register Option Register Not Used Data Register Data Direction Register Option Register Reserved Area (16 Bytes) OA1 Control Register OA2 Control Register OA3 Control Register OA Interrupt & Readout Register OA Voltage Reference Control Register Miscellaneous Register 1 Data I/O Register Control Register Status Register Watchdog Control register Clock, Reset and Supply Control / Status Register Reserved Area (11 Bytes) Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register Miscellaneous Register2 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W see Section 7.2.2 00h 00h 00h 00h 00h 00h xxh 0xh 00h 7Fh 00h R/W R/W R/W Section 7.3 R/W see Section 4.3.5 R/W R/W Read Only R/W R/W Reset Status 00h 00h 00h 00h 00h 00h 00h 00h 00h Remarks R/W R/W R/W Absent R/W R/W R/W Absent R/W R/W R/W
Port A
Port B
Port C
OPAMP
MISC1 SPI WDG CRS
TIMER16
MISC2
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Address 0041h to 004Fh 0050h 0051h 0052h 0053h 0054h 0055h to 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch to 007Fh
Block Name
Register Label
Register name Reserved Area (15 Bytes)
Reset Status
Remarks
SCI
SCISR SCIDR SCIBRR SCICR1 SCICR2
Status Register Data Register Baud Rate Register Control Register 1 Control Register 2 Reserved Area (27 Bytes)
0C0h 0xxh 0Xxh 0xxh 00h
Read Only R/W R/W R/W R/W
ADC
ADCDR ADCCSR
Data Register Control/Status Register Reserved Area (2 Bytes)
00h 00h
Read Only R/W
ART/PWM
PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1
PWM Duty Cycle Register 1 PWM Duty Cycle Register 0 PWM Control Register Control/Status Register Counter Access Register Auto Reload Register Input Capture Control Status Register Input Capture Register 1 Reserved Area (4 Bytes)
00h 00h 00h 00h 00h 00h 00h
R/W R/W R/W R/W R/W R/W R/W Read Only
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2 FLASH PROGRAM MEMORY
2.1 INTRODUCTION FLASH devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool) on a byte-bybyte basis. 2.2 MAIN FEATURES
s s s s
Remote In-Situ Programming (ISP) mode Up to 16 bytes programmed in the same cycle MTP memory (Multiple Time Programmable) Read-out memory protection against piracy
2.3 STRUCTURAL ORGANISATION The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area . 2.4 IN-SITU PROGRAMMING (ISP) MODE The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact. An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification. Remote ISP Overview The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin. The Remote ISP is performed in three steps: - Selection of the RAM execution mode - Download of Remote ISP code in RAM - Execution of Remote ISP code in RAM to program the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode, the ST7 has to be supplied with power (V DD and VSS) and a clock signal (oscillator and application crystal circuit for example).
This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are: - RESET: device reset - VSS: device ground power supply - ISPCLK: ISP output serial clock pin - ISPDATA: ISP input serial data pin - ISPSEL: Remote ISP mode selection. This pin must be connected to VSS on the application board through a pull-down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level. Figure 1 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description. Figure 5. Typical Remote ISP Interface XTAL
HE10 CONNECTOR TYPE TO PROGRAMMING TOOL
1 CL0 CL1
OSC2
OSC1
VDD
ISPSEL 10K VSS RESET
ST7
ISPCLK ISPDATA 47K
APPLICATION
2.5 MEMORY READ-OUT PROTECTION The read-out protection is enabled through an option bit. For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E2PROM data memory (when available) can be protected only with ROM devices.
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3 CENTRAL PROCESSING UNIT
3.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 3.2 MAIN FEATURES
s s s s s s s s
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
3.3 CPU REGISTERS The 6 CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions. Figure 6. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable
Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh
15 0 7 0 1 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 7). Since the stack is 128 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. Figure 7. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 7. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 017Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 017Fh Stack Lower Address = 0100h
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4 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 8. 4.1 Main Features
s
s s
s
Supply Manager - Main supply Low voltage detection (LVD)
s
- Global power down Reset Sequence Manager (RSM) Multi-Oscillator (MO) - 4 Crystal/Ceramic resonator oscillators - 2 External RC oscillators - 1 Internal RC oscillator Clock Security System (CSS) - Clock Filter - Backup Safe Oscillator Main Clock controller (MCC)
Figure 8. Clock, Reset and Supply Block Diagram
MCO CLOCK SECURITY SYSTEM (CSS) OSCOUT OSCIN MULTIOSCILLATOR (MO) FILTER OSC CLOCK SAFE
fCPU fOSC
MAIN CLOCK CONTROLLER (MCC)
RESET SEQUENCE RESET MANAGER (RSM) FROM WATCHDOG PERIPHERAL
V DD V SS
LOW VOLTAGE DETECTOR (LVD) -
LVD RF 0
CSS IE SOD
WDG RF
CRSR
CF INTERRUPT
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4.2 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the V DD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling The LVD function is illustrated in the Figure . Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: - under full software control - in static safe reset Figure 9. Low Voltage Detector vs Reset VDD In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: 1. The LVD allows the device to be used without any external RESET circuitry. 2. Three different reference levels are selectable through the option byte according to the application requirement. LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register. This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).
Vhyst VIT+ VIT-
RESET
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4.2.1 Reset Sequence Manager (RSM) The RSM block of the CROSS Module includes three RESET sources as shown in Figure 10: s EXTERNAL RESET SOURCE pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET
These sources act on the RESET PIN and it is always kept low during the READ OPTION RESET phase. The RESET service routine vector is fixed at the FFFEh-FFFFh addresses in the ST7 memory map.
Figure 10. Reset Block Diagram
VDD
fCPU
COUNTER
INTERNAL RESET
RON
RESET
WATCHDOG RESET READ OPTION RESET LVD RESET
The basic RESET sequence consists of 4 phases as shown in Figure 11: s OPTION BYTE reading to configure the device s Delay depending on the RESET source s 4096 cpu clock cycle delay s RESET vector fetch
The duration of the OPTION BYTE reading phase (tROB) is defined in the Electrical Characteristics section. This first phase is initiated by an external RESET pin pulse detection, a Watchdog RESET detection, or when VDD rises up to VLVDopt. The 4096 cpu clock cycle delay allows the oscillator to stabilise and to ensure that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. RESET Sequence Phases RESET
READ OPTION BYTE DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR
tROB
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RESET SEQUENCE MANAGER (Cont'd) 4.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least t h(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 12). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 12. RESET Sequences VDD
VIT+ VIT-
4.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDDLVD RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
RUN
DELAY
RUN
DELAY
RUN
DELAY
RUN
DELAY
RUN
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
th(RSTL)in
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (4096 TCPU) FETCH VECTOR
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4.2.4.1 Multi-Oscillator (MO) The Multi-Oscillator (MO) block is the main clock supplier of the ST7. To insure an optimum integration in the application, it is based on an external clock source and six different selectable oscillators. The main clock of the ST7 can be generated by 8 different sources comming from the MO block: s an External source s 4 Crystal or Ceramic resonator oscillators s 1 External RC oscillators s 1 Internal High Frequency RC oscillator Each oscillator is optimized for a given frequency range in term of consumption and is selectable through the Option Byte. External Clock Source The default Option Byte value selects the External Clock in the MO block. In this mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSCin pin while the OSCout pin is tied to ground (see Figure 13). Figure 13. MO External Clock
ST7 OSCin OSCout
EXTERNAL SOURCE
Crystal/Ceramic Oscillators This family of oscillators allows a high accuracy on the main clock of the ST7. The selection within the list of 4 oscillators has to be done by Option Byte according to the resonator frequency in order to reduce the consumption. In this mode of the MO block, the resonator and the load capacitors have to be connected as shown in Figure 14 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. These oscillators, when selected via the Option Byte, are not stopped during the RESET phase to avoid losing time in the oscillator starting phase. Figure 14. MO Crystal/Ceramic Resonator
ST7 OSCin OSCout
CL0
LOAD CAPACITORS
CL1
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MULTIOSCILLATOR (MO) (Cont'd) External RC Oscillator This oscillator allows a low cost solution on the main clock of the ST7 using only an external resistor and an external capacitor (see Figure 15). The selection of the external RC oscillator has to be done by Option Byte. The frequency of the external RC oscillator is fixed by the resistor and the capacitor values: N fOSC ~ REX . CEX The previous formula shows that in this MO mode, the accuracy of the clock is directly linked to the accuracy of the discrete components. Figure 15. MO External RC
ST7 OSCin OSCout
Internal RC Oscillator The Internal RC oscillator mode is based on the same principle as the External RC one including the an on-chip resistor and capacitor. This mode is the most cost effective one with the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz. In this mode, the two oscillator pins have to be tied to ground as shown in Figure 16. The selection of the internal RC oscillator has to be done by Option Byte. Figure 16. MO Internal RC
ST7 OSCin OSCout
REX
CEX
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4.3 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte. 4.3.1 Clock Filter Control The clock filter is based on a clock frequency limitation function. This filter function is able to detect and filter high frequency spikes on the ST7 main clock. If the oscillator is not working properly (e.g. working at a harmonic frequency of the resonator), the current active oscillator clock can be totally filtered, and then no clock signal is available for the ST7 from this oscillator anymore. If the original clock source recovers, the filtering is stopped automatically and the oscillator supplies the ST7 clock. 4.3.2 Safe Oscillator Control The safe oscillator of the CSS block is a low frequency back-up clock source (see Figure 17). If the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations. Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers. Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the CRSR register description. 4.3.3 Low Power Modes
Mode WAIT Description No effect on CSS. CSS interrupt cause the device to exit from Wait mode. The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET.
HALT
4.3.4 Interrupts The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event Enable Event Control Flag Bit CSSIE Exit from Wait Yes Exit from Halt1) No
CSS event detection (safe oscillator acti- CSSD vated as main clock)
Note 1: This interrupt allows to exit from active-halt mode if this mode is available in the MCU. Figure 17. Clock Filter Function and Safe Oscillator Function
CLOCK FILTER FUNCTION
fOSC/2 fCPU
SAFE OSCILLATOR FUNCTION
fOSC/2 fSFOSC fCPU
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4.3.5 Main Clock Controller (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows the power saving modes such as SLOW mode to be managed by the application. All functions are managed by the Miscellaneous Register 1 (MISCR1). The MCC block consists of: - a programmable CPU clock prescaler - a clock-out signal to supply external devices
The prescaler allows the selection of the main clock frequency and is controlled with three bits of the MISCR1: CP1, CP0 and SMS. The clock-out capability is an Alternate Function of an I/O port pin, providing the fCPU clock as an output for driving external devices. It is controlled by the MCO bit in the MISCR1 register.
Figure 18. Main Clock Controller (MCC) Block Diagram
OSCIN OSCOUT
MULTIOSCILLATOR (MO)
CLOCK FILTER (CF)
fOSC
DIV 2
DIV 2, 4, 8, 16
MISCR1
MCO CP1 CP0 SMS
CPU CLOCK TO CPU AND PERIPHERALS
fCPU
PORT MCO ALTERNATE FUNCTION
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4.4 CLOCK, RESET AND SUPPLY REGISTER DESCRIPTION CLOCK RESET AND SUPPLY (CRSR) Read /Write Reset Value: 000x 000x (00h)
7
REGISTER Bit 1 = CSSD CSS Safe Osc. Detection This bit indicates that the safe oscillator of the CSS block has been selected. It is set by hardware and cleared by reading the CRSR register when the original oscillator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated Bit 0 = WDGRF WatchDog Reset Flag This bit indicates when set that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset. Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LVDRF 0 0 1 WDGRF 0 1 X
0
-
-
-
LVD RF
-
CSS IE
CSS WDG D RF
Bit 7:5 = Reserved. Bit 4 = LVDRF LVD Reset Flag This bit indicates when set that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero) or a Watchdog Reset. See WDGRF flag description for more details. Bit 3 = Reserved. Bit 2 = CSSIE CSS Interrupt Enable This bit allows to enable the interrupt when a distrurbance is detected by the Clock Security System (CSSD bit set). It is set and cleared by software. 0: Clock Filter interrupt disable 1: Clock Filter interrupt enable
Table 3. Supply, Reset and Clock Register Map and Reset Values
Address (Hex.) 0020h 0025h Register Label MISCR Reset Value CRSR Reset Value 7 PEI3 0 0 6 PEI2 0 0 5 MCO 0 0 4 PEI1 0 LVDRF x 3 PEI0 0 0 2 CP1 0 CSSIE 0 1 CP0 0 CSSD 0 0 SMS 0 WDGRF x
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5 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 19. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 5.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 19. 5.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed before entering the edge/ level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 5.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - Writing "0" to the corresponding bit in the status register or - Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) Figure 19. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
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INTERRUPTS (Cont'd) Table 4. Interrupt Mapping
Source Block RESET TRAP ei0 ei1 CSS SPI Description Reset Software Ext. Interrupt ei0 Ext. Interrupt ei1 Clock Filter Interrupt Transfer Complete Mode Fault Input Capture 1 Output Compare 1 Input Capture 2 Output Compare 2 Timer Overflow Input Capture 1 Timer Overflow OA1 Interrupt OA2 Interrupt Register Label N/A N/A N/A N/A CRSR SPISR Flag N/A N/A N/A N/A CSSD SPIF MODF ICF1_1 OCF1_1 ICF2_1 OCF2_1 TOF_1 ICF0 OVF OA1V OA2V Exit from HALT yes no yes yes no no Vector Address FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h Priority Order Highest Priority
TIMER 16
TASR
no
FFF2h-FFF3h
ART/PWM OP-AMP
ARTICCSR ARTCSR OIRR
yes yes
SCI
NOT USED SCI Peripheral Interrupts NOT USED
no
FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE6-FFE9 FFE4-FFE5 FFE0h-FFE3h Lowest Priority
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6 POWER SAVING MODES
6.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 20). After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f CPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the the oscillator status. Figure 20. Power Saving Mode Transitions
High RUN
6.2 SLOW MODE This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when enterring the WAIT mode while the device is already in SLOW mode. Figure 21. SLOW Mode Clock Transitions
fOSC/4 fCPU fOSC/8 fOSC/2
fOSC/2 MISCR1
SLOW WAIT SLOW WAIT HALT Low POWER CONSUMPTION
CP1:0 SMS
00
01
NEW SLOW FREQUENCY REQUEST
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 6.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register are forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 22. Figure 22. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0
WFI INSTRUCTION
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 1 Y
4096 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CPU I BIT (see note)
ON ON ON 1
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 6.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 24). The MCU can exit HALT mode on reception of either an specific interrupt (see Table 4, "Interrupt Mapping," on page 26) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 23). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 11.1 OPTION BYTES for more details). Figure 23. HALT Mode Timing Overview
RUN HALT 4096 CPU CYCLE DELAY RUN
Figure 24. HALT Mode Flow-chart
HALT INSTRUCTION ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF 0 I BIT 0 WATCHDOG DISABLE
N RESET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 1
4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BIT 4) ON ON ON 1
FETCH RESET VECTOR OR SERVICE INTERRUPT HALT INSTRUCTION
RESET OR INTERRUPT
FETCH VECTOR
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 4, "Interrupt Mapping," on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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7 ON-CHIP PERIPHERALS
7.1 I/O PORTS 7.1.1 Introduction The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - analog signal input (ADC) - alternate signal input/output for the on-chip peripherals. - external interrupt generation An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 7.1.2 Functional Description Each port is associated to 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and some of them to an optional register (see register description): - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, for specific ports which do not provide this register refer to the I/O Port Implementation Section 7.1.2.5. The generic I/O block diagram is shown on Figure 26. 7.1.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. All the inputs are triggered by a Schmitt trigger. 2. When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register (where available). Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, it masks the other ones. 7.1.2.2 Output Mode The pin is configured in output mode by setting the corresponding DDR register bit. In this mode, writing "0" or "1" to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Note: In this mode, the interrupt function is disabled. 7.1.2.3 Digital Alternate Function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
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I/O PORTS (Cont'd) 7.1.2.4 Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings. 7.1.2.5 I/O Port Implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input (see Figure 26) or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 25. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 25. Recommended I/O State Transition Diagram
INPUT with interrupt
INPUT no interrupt
OUTPUT open-drain
OUTPUT push-pull
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I/O PORTS (Cont'd) Figure 26. I/O Block Diagram
ALTERNATE ENABLE ALTERNATE 1 M OUTPUT U X 0 VDD P-BUFFER (SEE TABLE BELOW) PULL-UP (SEE TABLE BELOW)
DR LATCH DATA BUS COMMON ANALOG RAIL DDR LATCH OR LATCH (SEE TABLE BELOW)
ALTERNATE ENABLE PULL-UP CONDITION
PAD ANALOG ENABLE (ADC) ANALOG SWITCH (SEE NOTE BELOW)
OR SEL
DDR SEL N-BUFFER DR SEL 1 M U X0 ALTERNATE ENABLE
GND
ALTERNATE INPUT
CMOS EXTERNAL INTERRUPT SOURCE (EIx) SENSITIVITY SEL FROM OTHER BITS SCHMITT TRIGGER
Table 5. Port Mode Configuration
Configuration Mode Floating Pull-up Push-pull True Open Drain Open Drain (logic level) Legend: 0present, not activated 1present and activated Pull-up 0 1 0 not present 0 P-buffer 0 0 1 not present 0
Notes: - No OR Register on some ports (see register map). - ADC Switch on ports with analog alternate functions.
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I/O PORTS (Cont'd) 7.1.2.6 Device Specific Configurations Table 6. Port Configuration
Port Pin name OR = 0 floating* Input (DDR =0) OR = 1 pull-up with interrupt Output (DDR=1) OR = 0 OR = 1 open drain open drain high sink capability open drain open drain push-pull
Port A
PA7: PA0
PB0:PB4 Port B PB5:PB7 Port C PC0:PC5
floating* floating* floating*
pull-up with interrupt pull-up with interrupt pull-up
push-pull push-pull push-pull
*Reset state.
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I/O PORTS (Cont'd) 7.1.3 Register Description DATA REGISTERS Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Read /Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0 O7 O6 O5 O4 O3 O2 O1 O0
OPTION REGISTERS PORT A Option Register (PAOR) PORT B Option Register (PBOR) PORT C Option Register (PCOR) Read/Write Reset Value: 0000 0000 (00h) (no interrupt)
7 0
Bit 7:0 = D[7:0] Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken in account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTERS Port A Data Direction Register (PADDR) Port B Data Direction Register (PBDDR) Port C Data Direction Register (PCDDR) Read/Write Reset Value: 0000 0000 (00h) (input mode)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bit 7:0 = O[7:0] Option Register 8 bits. The PAOR, PBOR and PCOR registers are used to select pull-up or floating configuration in input mode. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Input pull-up (with or without interrupt see Table 6)
Bit 7:0 = DD[7:0] Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 7. I/O Port Register Map and Reset Values
Address (Hex.) 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah Register Label PADR Reset Value PADDR Reset Value PAOR Reset Value PBDR Reset Value PBDDR Reset Value PBOR Reset Value PCDR Reset Value PCDDR Reset Value PCOR Reset Value 7 D7 0 D7 0 D7 0 D7 0 DD7 0 O7 0 D7 0 DD7 0 O7 0 6 D6 0 D6 0 D6 0 D6 0 DD6 0 O6 0 D6 0 DD6 0 O6 0 5 D5 0 D5 0 D5 0 D5 0 DD5 0 O5 0 D5 0 DD5 0 O5 0 4 D4 0 DD4 0 O4 0 D4 0 DD4 0 O4 0 D4 0 DD4 0 O4 0 3 D3 0 DD3 0 O3 0 D3 0 DD3 0 O3 0 D3 0 DD3 0 O3 0 2 D2 0 DD2 0 O2 0 D2 0 DD2 0 O2 0 D2 0 DD2 0 O2 0 1 D1 0 DD1 0 O1 0 D1 0 DD1 0 O1 0 D1 0 DD1 0 O1 0 0 D0 0 DD0 0 O0 0 D0 0 DD0 0 O0 0 D0 0 DD0 0 O0 0
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7.2 MISCELLANEOUS REGISTERS 7.2.1 Miscellaneous Register 1 (MISCR1) Miscellaneous register 1 is used select SLOW operating mode. Bits 3, 4, 6, and 7 determine the polarity of external interrupt requests. Register Address: 0020h -- Read /Write Reset Value: 0000 0000 (00h)
7 0
Bit 4:3 = PEI[1:0] Polarity Options of External Interrupt ei0. (Port A) These bits determine which event causes the external interrupt (ei0) on port A according to Table 9. Table 9. ei0 Ext. Int. Polarity Options
MODE Falling edge and low level (Reset state) Rising edge only PEI1 0 0 1 1 PEI0 0 1 0 1
PEI3
PEI2
MCO PEI1 PEI0 CP1
CP0 SMS
Bit 7:6 = PEI[3:2] Polarity Options of External Interrupt ei1. (Port B). These bits are set and cleared by software. These bits determine which event causes the external interrupt (ei1) on port B according to Table 8. Table 8. ei1 Ext. Int. Polarity Options
MODE Falling edge and low level (Reset state) Rising edge only Falling edge only Rising and falling edge PEI3 0 0 1 1 PEI2 0 1 0 1
Falling edge only Rising and falling edge
Bit 2:1 = CP[1:0] CPU clock prescaler These bits are set and cleared by software. They determine the CPU clock when the SMS bit is set according to the following table. Table 10. fCPU Value in Slow Mode fCPU Value
fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 CP1 0 1 0 1 CP0 0 0 1 1
Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fOSC/2 on I/O port) This bit is set and cleared by software. When set it can be used to output the internal clock to the dedicated I/O port.
Bit 0 = SMS Slow Mode Select This bit is set and cleared by software. 0: Normal Mode - fCPU = fOSC/ 2 1: Slow Mode - the fCPU value is determined by the PC[1:0] bits.
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7.2.2 Miscellaneous Register 2 (MISCR2) Miscellaneous register 2 is used to configure of SPI and the output selection of the PWMs. Register Address: 0040h -- Read /Write Reset Value: 0000 0000 (00h)
7 0
floating input. This should be done prior to setting the P1OS bit. Bit 2 = P0OS PWM0 output select This bit is used to select the output for the PWM0 channel of ART/PWM Timer. 0: PWM0 output on PWM0 pin 1: PWM0 output on PWM0R pin and connected to the OA1PIN pin Note: In order to use the PC2 port pin as a PWM output pin, bit 2 of port C must be programmed as floating input. This should be done prior to setting the P0OS bit. Bit 1 = SSM SS mode selection It is set and cleared by software. 0: Normal mode - SS uses information coming from the SS pin of the SPI. 1: I/O mode, the SPI uses the information stored into bit SSI. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software.
-
-
-
SPIOD P1OS P0OS SSM SSI
Bit 7:5 = not used Bit 4 = SPIOD SPI output disable This bit is used to disable the SPI output on the I/O port (in both master or slave mode). 0: SPI output enabled 1: SPI output disabled (I/O pin free for general-purpose I/O) Bit 3 = P1OS PWM1 output select This bit is used to select the output for the PWM1 channel of the ART/PWM Timer. 0: PWM1 output on PWM1 pin 1: PWM1 output on PWM1R pin and connected to the OA2PIN pin Note: In order to use the PC1 port pin as a PWM output pin, bit 1 of port C must be programmed as
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7.3 OP-AMP MODULE 7.3.1 Introduction The ST7 Op-Amp module is designed to cover most types of microcontroller applications where analog signal amplifiers are used. It may be used to perform a a variety of functions such as: differential voltage amplifier, comparator/ threshold detector, ADC zooming, impedance adaptor, general purpose operational amplifier. 7.3.2 Main features This module includes: s 2 rail-to-rail SPGAs (Software Programmable Gain Amplifier), and 1 stand alone rail-to-rail Op-Amp that may be externally connected using I/O pins s A band gap voltage reference s A programmable eight-step reference voltage s ART Timer PWM outputs internally connected to SPGAs input 1 and 2. s SPGAs and Op-Amp outputs are internally connected to the ADC inputs (Channel 8, 9 & 10). s Input offset compensation 7.3.3 General description The module contains two SPGAs (OA1 & OA2) and 1 stand alone operational amplifier (OA3) depending on the device package. OA1 and OA2 each have associated circuitry for input and gain selection. The third operational amplifier, OA3, without input and gain selection circuitry, is available in some devices (see device pin out description). 7.3.3.1 Inputs The non-inverting input of OA1 or OA2 may be connected to an I/O pin, to the band-gap reference voltage, to an 8-step voltage reference or to the analog ground. The eight-step voltage reference uses a resistive network in order to generate two voltages between 1/8 VDD and VDD (in 1/8 V DD steps) that can be connected to the non-inverting input of the two SPGAs. These voltages may be used as programmable thresholds with the corresponding SPGA used as a comparator or, with the SPGA programmed to have a gain of 2, 4 or 8, they may be used for extending the ADC precision (analog zooming). The 2 inverting inputs of OA1 or OA2 may be used to achieve this function. The input impedance of these inputs is around 2K. The ART Timer PWM resistive outputs are internally connected to OA1PIN and OA2PIN pins. The PWM outputs are enabled by the PWMCR register and the resistive outputs are selected by Miscellaneous register 2. Refer to Figure 28. The inverting input of OA1 or OA2 may be connected to an I/O pin, to the analog ground or may be left unconnected (in this case the SPGA can be used as a repeater, with the output of the SPGA connected to this input via the resistive loopback). 7.3.3.2 Outputs The SPGA outputs are connected either to external pins or, internally, to the ADC input (Channel 8 & 9). The output value, digitized by a Schmitt trigger, may be read by the application software or may generate an interrupt. The OA3 output is connected to an ADC input (Channel 10). 7.3.3.3 Advanced features The gain of OA1 or OA2 is programmed using an internal resistive network. The possible values are: 1, 2, 4, 8 and 16. The internal resistive loopback may also be de-activated in order to obtain the open-loop gain (comparator) or to use the op-amp with an external loopback network. Input offset compensation In a special calibration mode (autozero mode), the negative input pin of OA1 or OA2 can be connected internally to the positive input pin. This mode allows the measurement of the input offset voltage of the SPGA using the ADC. This value may be stored in RAM and subsequently used for offset correction (for ADC conversions). Refer to Section 9.3.4.
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OP-AMP MODULE (Cont'd) Figure 27. Op-Amp Module Block Diagram
NS1[2:0] bits OA1NIN VSSA 15R /16R ART Timer PWM0R Output R=2K AZ1 bit AVCL=1, 2, 4, 8, 16, R G1[2:0] bits
To ADC Channel 8
VR1E, PS1[1:0] bits OA1PIN R=2K OA1
OA1O Band Gap Reference Voltage (1.2V) VR1[2:0] bits x VDDA/8 8-Step Reference Voltage 1 NS2[2:0] bits OA2NIN VSSA ART Timer PWM1R Output R=2K AZ2 bit AVCL=1, 2, 4, 8, 16, G2[2:0] bits 15R /16R R OA1V bit OA1IE bit OA1 Interrupt
To ADC Channel 9
VR2E, PS2[1:0] bits OA2PIN R=2K OA2
OA2O Band Gap Reference Voltage (1.2V) OA3NIN OA3 OA3PIN OA3O VR2[2:0] bits x VDDA/8 8-Step Reference Voltage 2 OA2V bit OA2IE bit OA2 Interrupt
To ADC Channel 10
Note: OA3 is not present on some package types. Refer to the device pin description.
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OP-AMP MODULE (Cont'd) 7.3.4 Autozero Mode When the following description refers to both OA1 or OA2, x stands for 1 or 2. In order to eliminate the ADC errors due to the SPGA offset voltage, this voltage may be determined, prior to the A/D conversion (at power on or periodically) and stored in RAM. The stored value may be used afterwards to eliminate the errors of any A/D conversion that uses the SPGA (ADC zooming). The measurement may be done independently for OA1 and OA2. The measurement algorithm has 3 steps: 1. The SPGA is in repeater mode (NSx[1:0] = 01), with the lowest gain (Gx[2:0]=000), the autozeroing switch is left open (AZx = 0). The positive input of the op-amp is connected to a DC value, using the VRx reference voltage generator (PSx[1:0] = 00), and the output is sent to the ADC. Under these conditions, the ADC measures the value: Vo = VRx -Voff of the SPGA output. 2. Set the gain (G) according the application requirement. The AZx bit is set to 1. The output voltage of the SPGA becomes: V'o = VRx - Voff - G * Voff 3.Voff calculated with 1) - 2)
Voff =( Vo- V'o) /G As the offset voltage of the SPGAs may vary with the common mode voltage value, the measurement must be done choosing VRx to match the application conditions. Alternatively, nine measurements may be done with the noninverting input voltage varying between 0 and VDDA in 1/8 V DD steps, in order to fully characterise the offset voltage of the op-amp. 7.3.5 Comparator mode with Interrupts The 2 SPGAs can be configured in comparator mode (GX[2:0]=111). In this case the positive input can be connected to the internal reference voltage. The negative input can be used to receive the analog voltage to be compared with the voltage connected to the positive input. By means of a Schmitt trigger, the SPGA output is readable as a logical level in the OAxVR bit in the OAIRR register. These bits are read only. An interrupt request remains pending as long as the output value (OAxVR) is equal to the corresponding polarity bit (OAxPR) and when the interrupt enable bit (OAxIE) is set. There is one interrupt vector for each SPGA.
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OP-AMP MODULE (Cont'd) 7.3.6 DAC Function using ART Timer PWMR Outputs The PWMR outputs are connected to a serial resistor and internally connected to the OA1PIN/ OA2PIN inputs. An external capacitor must be connected to the PWM0R/OA1PIN and/or PWM1R/OA2PIN pins (see Figure 28) if the PWMR outputs are used.
This feature allows the microcontroller to be used as a Digital to Analog converter and generating a DC voltage on the positive input pin, so the SPGAs may be used for the following functions: - A comparator - An amplifier of an external voltage connected to the negative input pin (OA1NIN or OA2NIN). - A repeater, to obtain the same voltage on the OA output pin as on the input pin, with increased current capability.
Figure 28. Connection of PWMR outputs to OA1 or OA2 for DAC Function MISC2 REGISTER
P1OSP0OS
PWMCR REGISTER
OE1 OE0
PWM0R/OA1PIN Cext
0.7K (typ) R int
PWM0
PWM/ART TIMER
OA1
P1OS OE1
PWM1R/OA2PIN Cext
0.7K (max) Rint
PWM1 OA2
OPAMP MODULE
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OP-AMP MODULE (Cont'd) 7.3.7 Low Power Modes
Mode WAIT HALT Description No effect on op-amp. SPGA interrupts cause the device to exit from WAIT mode. No effect on op-amp. SPGA interrupts cause the device to exit from HALT mode.
Note: Low Power modes have no effect on the SPGAs & the Op-Amp. They can be switched off to reduce the power consumption of the ST7 (OAxON bits). 7.3.8 Interrupts
Interrupt Event Op-Amp 1 output in comparator mode equals to OA1P bit value Op-Amp 2 output in comparator mode equals to OA2P bit value Event Flag NA* NA* Enable Control Bit OA1IE OA2IE Exit from Wait Yes Yes Exit from Halt Yes Yes
* The interrupt event occurs when the OAxP bit equals the OAxV bit value. Note: The SPGA interrupt events are connected to 2 interrupt vectors (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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7.3.9 Register Description OA1 CONTROL REGISTER (OA1CR) Read/Write Reset value: 0000 00000 (00h)
7
AZ1 G12 G11 G10 PS11 PS10 NS11
Bit 1:0 = NS1[1:0] Negative Input Select. These bits are set and reset by software and control the OA1 positive input selection.
0
NS10
OA1 Negative Input AGND Floating - Repeater mode OA1NIN
NS11 0 0 1
NS10 0 1 X
Bit 7 = AZ1 OA1 Autozero Mode. This bit is set and reset by hardware. It enables Autozero mode (used to measure the OA1 input offset). 0: Autozero mode disabled 1: Autozero mode enabled Bit 6:4 = G1[2:0] Gain Control. These bits are set and reset by software and control the OA1 gain by modifying the resistive loopback network. The value of the gain is adjusted to the desired value (for inverting / non-inverting amplification) corresponding to the selected positive input source - see PS1[1:0] table, Gain Adjust column.
Gain inv / Ninv -1 / 2 -2 / 3 -3 / 4 -4 / 5 -8 / 8 -16 / 16 Comparator External Loopback G12 0 0 0 0 1 1 1 G11 0 0 1 1 0 0 1 G10 0 1 0 1 0 1 1
OA2 CONTROL REGISTER (OA2CR) Read/Write Reset value: 0000 0000 (00h)
7
AZ2 G22 G21 G20 PS21 PS20 NS21
0
NS20
Bit 7 = AZ2 OA2 Autozero Mode. This bit is set and reset by hardware. It enables Autozero mode (used to measure the OA2 input offset). 0: Autozero mode disabled 1: Autozero mode enabled Bit 6:4 = G2[2:0] Gain Control. These bits are set and reset by software and control the OA2 gain by modifying the resistive loopback network. The value of the gain is adjusted to the desired value (for inverting/noninverting amplification) corresponding to the selected positive input source - see PS2[1:0] table, Gain Adjust column.
Gain inv / Ninv -1 / 2 -2 / 3 -3 / 4 -4 / 5 -8 / 8 -16 / 16 Comparator External Loopback G22 0 0 0 0 1 1 1 G21 0 0 1 1 0 0 1 G20 0 1 0 1 0 1 1
Bit 3:2 = PS1[1:0] Positive Input Select / Gain adjust. These bits are set and reset by software and control the OA1 positive input selection.
OA1 Positive Input 8-step Ref.Voltage 1 OA1PIN Band Gap Ref. Voltage (1.2V) Gain Adj. inv ninv inv PS11 PS10 0 0 1 0 1 0
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OP-AMP MODULE (Cont'd) Bit 3:2 = PS2[1:0] Positive Input Select / Gain adjust. These bits are set and reset by software and control the OA2 positive input selection.t
OA2 Positive Input 8-step Ref.Voltage 1 OA2PIN Band Gap Ref. Voltage (1.2V) Floating Gain Adj. inv ninv inv ninv PS21 PS20
OA3 CONTROL REGISTER (OA3CR) Read/Write Reset value: 0000 0000 (00h)
7
OA3ON -
0
-
0 0 1 1
0 1 0 1
Bit 1:0 = NS2[1:0] Negative Input Select. These bits are set and reset by software and control the OA2 negative input selection.
OA2 Negative Input AGND Floating -Repeater mode OA2NIN NS21 0 0 1 NS20 0 1 X
Bit 7 = OA3ON OA3 on/off (low power) Stand Alone Op-Amp on/off control bit, it is set and reset by software. It reduces power consumption when reset. 0: Op-amp 3 off 1: Op-amp 3 on Note: This bit must be kept cleared in devices without OA3 (refer to device block diagram and pin description) Bit 6:0 = Reserved.
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OP-AMP MODULE (Cont'd) OP-AMP INTERRUPT AND READOUT REGISTER (OAIRR) Read/Write* Reset value: 0000 0000 (00h)
7
OA1IE OA1P OA1V OA1ON OA2IE OA2P
0
OA2V OA2ON
Bit 3 = OA2IE OA2 interrupt enable This bit is set and reset by software. When it is set, it enables an interrupt to be generated if the OA2P bit and the OA2V bit have the same value. 0: OA2 interrupt disabled 1: OA2 interrupt enabled Bit 2 = OA2P OA2 interrupt polarity select This bit is set and reset by software. It specifies the OA2 SPGA output level which will generate an interrupt if the bit OA2IE is set. 0: Active low 1: Active high Bit 1- OA2V OA2 output value (read only) This bit is set and reset by hardware. It contains the OA2 SPGA output voltage value filtered by a Schmitt trigger. 0: OA2+ voltage < OA2- voltage 1: OA2+ voltage > OA2- voltage Bit 0 - OA2ON OA2 on/off (low power) 0: Op-amp 2 off (reducing power consumption) 1: Op-amp 2 on Note: If OA1ON, OA2ON and OA3ON are 0, The entire module is disabled, giving the lowest power consumption. * OA1V and OA2V are read only.
Bit 7 = OA1IE OA1 interrupt enable This bit is set and reset by software. When it is set, it enables an interrupt to be generated if the OA1P bit and the OA1V bit have the same value. 0: OA1 interrupt disabled 1: OA1 interrupt enabled Bit 6 = OA1P OA1 interrupt polarity select This bit is set and reset by software. It specifies the OA1 SPGA output level which will generate an interrupt if the bit OA1IE is set. 0: Active low 1: Active high Bit 5 = OA1V OA1 output value (read only) This bit is set and reset by hardware. It contains the OA1 SPGA output voltage value filtered by a Schmitt trigger. 0: OA1+ voltage < OA1- voltage 1: OA1+ voltage > OA1- voltage Bit 4 = OA1ON OA1 on/off (low power) This bit is set and reset by software. It reduces power consumption when reset. 0: Op-amp 1 off 1: Op-amp 1 on
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OP-AMP MODULE (Cont'd) VOLTAGE REFERENCE CONTROL REGISTER (OAVRCR) Read/Write Reset value: 0000 0000 (00h)
7
VR2E VR22 VR21 VR20 VR1E VR12 VR11
0
VR10
Bit 7 = VR2E: VR2 Enable This bit is set and reset by software. When the refererence voltage is selected (PS2[1:0] = 00 in the OA2CR register) it connects V SSA (analog ground) or Reference Voltage 2 (VR2) to the OA2 positive input. 0: OA2 positive input is connected to V SSA 1: OA2 positive input is connected to VR2 voltage value Bit 6:4 = VR2[2:0] Voltage selection for channel 2 of the 8-step reference voltage These bits are set and reset by software, they specify the Reference Voltage 2 (VR2) connected to the OA2 positive input when PS2[1:0] = 00 in the OA2CR register..
Reference Voltage 2 0 (VSSA ) VDDA/8 2 x VDDA/8 3 x VDDA/8 4 x VDDA/8 5 x VDDA/8 6 x VDDA/8 7 x VDDA/8 VDDA VR2E 0 1 1 1 1 1 1 1 1 VR22 x 0 0 0 0 1 1 1 1 VR21 x 0 0 1 1 0 0 1 1 VR20 x 0 1 0 1 0 1 0 1
Bit 3= VR1E VR1 Enable This bit is set and reset by software. When the refererence voltage is selected (PS1[1:0] = 00 in the OA1CR register) it connects VSSA (analog ground) or Reference Voltage 1 (VR1) to the OA1 positive input. 0: OA1 positive input is connected to VSSA 1: OA1 positive input is connected to VR1 voltage value Bit 2:0 - VR1[2:0] Voltage selection for channel 1 of the 8-step reference voltage These bits are set and reset by software, they specify the Reference Voltage 1 (VR1) connected to the OA1 positive input when PS1[1:0] = 00 in the OA1CR register.
Reference Voltage 1 0 (VSSA) VDDA/8 2 x VDDA/8 3 x VDDA/8 4 x VDDA/8 5 x VDDA/8 6 x VDDA/8 7 x VDDA/8 VDDA VR1E 0 1 1 1 1 1 1 1 1 VR12 x 0 0 0 0 1 1 1 1 VR11 x 0 0 1 1 0 0 1 1 VR10 x 0 1 0 1 0 1
Note: When both VR2E and VR1E are reset, the 8-step voltage reference cell is disabled and enters low power mode.
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Table 11. OP-AMP Module Register Map and Reset Values
Address (Hex.) 001Bh 001Ch 001Dh 001Eh 001Fh Register Label OA1CR Reset Value OA2CR Reset Value OA3CR Reset Value OIRR Reset Value VRCR Reset Value 7 AZ1 0 AZ2 0 OA3ON 0 OA1IE 0 VR2E 0 6 G12 0 G22 0 0 OA1P 0 VR22 0 5 G11 0 G21 0 0 OA1V 0 VR21 0 4 G10 0 G20 0 0 OA2ON 0 VR20 0 3 PS11 0 PS21 0 0 OA2IE 0 VR1E 0 2 PS10 0 PS20 0 0 OA2P 0 VR12 0 1 NS11 0 NS21 0 0 OA2V 0 VR11 0 0 NS10 0 NS20 0 0 OA1ON 0 VR10 0
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7.4 WATCHDOG TIMER (WDG) 7.4.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 7.4.2 Main Features s Programmable timer (64 increments of 12288 CPU cycles) s Programmable reset s Reset (if watchdog activated) when the T6 bit reaches zero s Optional reset on HALT instruction (configurable by option byte) s Hardware Watchdog selectable by option byte. 7.4.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12,288 machine cyFigure 29. Watchdog Block Diagram cles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 13 . Watchdog Timing (fCPU = 8 MHz)): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset.
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /12288
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WATCHDOG TIMER (Cont'd) Table 12. Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 7.4.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte description. 7.4.5 Low Power Modes WAIT Instruction No effect on Watchdog. HALT Instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). 7.4.5.1 Using Halt Mode with the WDG (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcontroller. - When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 7.4.6 Interrupts None. 7.4.7 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
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WATCHDOG TIMER (Cont'd) Table 13. WDG Register Map
Address (Hex.) 24 Register Name CR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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7.5 16-BIT TIMER 7.5.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 7.5.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse Width Modulation mode (PWM) s One Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 1. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 7.5.3 Functional Description 7.5.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 1. The value in the counter register repeats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 30. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE
8 high
8 low
8-bit buffer
8 high low
8 high
8 low
8 high
8 low
8 high
8 low
8
EXEDG
16
1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2
16
16
16
CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1 pin
6
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Read MS Byte Other instructions Read At t0 +t LS Byte
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 7.5.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 31. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 32. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 33. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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16-BIT TIMER (Cont'd) 7.5.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 1). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as a floating input).
When an input capture occurs: - The ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 6). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 34. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 35. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 7.5.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCIE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
fCPU
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1)
If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 1). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 8). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 9). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 36. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode.
16 BIT FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
16-bit
OUTPUT COMPARE CIRCUIT
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
16-bit
16-bit
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 37. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 38. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 7.5.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 1).
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 10). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.
One Pulse mode cycle
When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 39. One Pulse Mode Timing Example
COUNTER ICAP1 OCMP1
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 40. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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16-BIT TIMER (Cont'd) 7.5.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 1). If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 11) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.
Pulse Width Modulation cycle
When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
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16-BIT TIMER (Cont'd) 7.5.4 Low Power Modes
Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
7.5.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 7.5.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode
1) 2)
Input Capture 1 Yes Yes No No
AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes 1) No Partially 2) Not Recommended 3) Not Recommended No No
See note 4 in Section 0.1.3.5 One Pulse Mode See note 5 in Section 0.1.3.5 One Pulse Mode 3) See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode
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16-BIT TIMER (Cont'd) 7.5.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 14. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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Table 15. 16-Bit Timer Register Map and Reset Values
Address (Hex.) 0032h 0031h 0033h Register Name CR1 Reset Value CR2 Reset Value SR Reset Value IC1HR 0034h0035h Reset Value IC1LR Reset Value OC1HR 0036h0037h Reset Value OC1LR Reset Value OC2HR 003Eh003Fh Reset Value OC2LR Reset Value CHR 0038h0039h Reset Value CLR Reset Value ACHR 003Ah003Bh Reset Value ACLR Reset Value IC2HR 003Ch003Dh Reset Value IC2LR Reset Value 7 ICIE 0 OC1E 0 ICF1 0 MSB MSB MSB 1 MSB 0 MSB 1 MSB 0 MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 0 0 0 0 0 1 1 1 1 5 TOIE 0 OPM 0 TOF 0 0 0 0 0 1 1 1 1 4 FOLV2 0 PWM 0 ICF2 0 0 0 0 0 1 1 1 1 3 FOLV1 0 CC1 0 OCF2 0 0 0 0 0 1 1 1 1 2 OLVL2 0 CC0 0 0 0 0 0 0 1 1 1 1 1 IEDG1 0 IEDG2 0 0 0 0 0 0 1 0 1 0 0 OLVL1 0 EXEDG 0 0 LSB LSB LSB 0 LSB 0 LSB 0 LSB 0 LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB -
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7.6 PWM AUTO-RELOAD TIMER (ART) 7.6.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: - Generation of up to 4 independent PWM signals - Output compare and Time base interrupt Figure 41. PWM Auto-Reload Timer Block Diagram
PWMCR OEx OPx OCRx REGISTER LOAD PWMx PORT ALTERNATE FUNCTION POLARITY CONTROL COMPARE DCRx REGISTER
- Up to two input capture functions - External event detector - Up to two external interrupt sources The three first modes can be used together with a single counter frequency. The timer can be used to wake up the MCU from WAIT and HALT modes.
ARR REGISTER
8-BIT COUNTER (CAR REGISTER)
LOAD
ARTICx
INPUT CAPTURE CONTROL
LOAD
ICRx REGISTER
ICSx
ICIEx
ICFx
ICCSR
ARTCLK
fEXT fCPU fCOUNTER
ICx INTERRUPT
MUX fINPUT
PROGRAMMABLE PRESCALER
EXCL
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR
OVF INTERRUPT
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PWM AUTO-RELOAD TIMER (Cont'd) 7.6.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (CAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARR register (the prescaler is not affected). Counter clock and prescaler The counter clock frequency is given by: fCOUNTER = fINPUT / 2CC[2:0] The timer counter's input clock (fINPUT) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (CSR). Thus the division factor of the prescaler can be set to 2 n (where n = 0, 1,..7). This fINPUT frequency source is selected through the EXCL bit of the CSR register and can be either the fCPU or an external input frequency fEXT. The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the CSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source. Counter and Prescaler Initialization After RESET, the counter and the prescaler are cleared and fINPUT = fCPU. The counter can be initialized by: - Writing to the ARR register and then setting the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the CSR register. - Writing to the CAR counter access register, In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. Direct access to the prescaler is not possible. Output compare control The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (DCRx) at each overflow of the counter. This double buffering method avoids glitch generation when changing the duty cycle on the fly.
Figure 42. Output compare control
fCOUNTER ARR=FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh FFh
OCRx
FDh
FEh
DCRx
FDh
FEh
PWMx
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PWM AUTO-RELOAD TIMER (Cont'd) Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function. The PWM signals all have the same frequency which is controlled by the counter period and the ARR register value. fPWM = fCOUNTER / (256 - ARR) When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding Figure 43. PWM Auto-reload Timer Function
255 DUTY CYCLE REGISTER (DCRx)
OPx (output polarity) bit in the PWMCR register. When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored. It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the contents of the ARR register. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (256 - ARR) Note: To get the maximum resolution (1/256), the ARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.
COUNTER
AUTO-RELOAD REGISTER (ARR) 000
t
PWMx OUTPUT
WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1
Figure 44. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER ARR=FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh
OCRx=FCh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FDh OCRx=FEh OCRx=FFh
t
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PWM AUTO-RELOAD TIMER (Cont'd) Output compare and Time base interrupt On overflow, the OVF flag of the CSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the CSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application. External clock and event detector mode Using the fEXT external prescaler input clock, the auto-reload timer can be used as an external clock event detector. In this mode, the ARR register is used to select the nEVENT number of events to be counted before setting the OVF flag. nEVENT = 256 - ARR When entering HALT mode while fEXT is selected, all the timer control registers are frozen but the counter continues to increment. If the OIE bit is set, the next overflow of the counter will generate an interrupt which wakes up the MCU.
Figure 45. External Event Detector Example (3 counts)
fEXT=f COUNTER ARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
CSR READ INTERRUPT IF OIE=1 INTERRUPT IF OIE=1
CSR READ
t
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PWM AUTO-RELOAD TIMER (Cont'd) Input capture function This mode allows the measurement of external signal pulse widths through ICRx registers. Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ICCSR). These input capture interrupts are enabled through the CIEx bits of the ICCSR register. The active transition (falling or rising edge) is software programmable through the CSx bits of the ICCSR register. The read only input capture registers (ICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ICCSR register). After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source. Note: After a capture detection, data transfer in the ICRx register is inhibited until it is read (clearing the CFx bit). The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled (CIEx bit set). This means, the ICRx register has to be read at each capture event to clear the CFx flag. The timing resolution is given by auto-reload counter cycle time (1/fCOUNTER ). Note: During HALT mode, if both input capture and external clock are enabled, the ICRx register value is not guaranteed if the input capture pin and the external clock change simultaneously. Figure 46. Input Capture Timing Diagram
f COUNTER
External interrupt capability This mode allows the Input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal. The edge sensitivity of the external interrupts is programmable (CSx bit of ICCSR register) and they are independently enabled through CIEx bits of the ICCSR register. After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source. During HALT mode, the external interrupts can be used to wake up the micro (if the CIEx bit is set).
COUNTER
01h
02h
03h
04h
05h
06h
07h
ARTICx PIN CFx FLAG xxh ICRx REGISTER
INTERRUPT
04h
t
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PWM AUTO-RELOAD TIMER (Cont'd) 7.6.3 Register Description CONTROL / STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h)
7 EXCL CC2 CC1 CC0 TCE FCRL OIE 0 OVF
COUNTER ACCESS REGISTER (CAR) Read /Write Reset Value: 0000 0000 (00h)
7 CA7 CA6 CA5 CA4 CA3 CA2 CA1 0 CA0
Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock. Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from f INPUT.
fCOUNTER fINPUT fINPUT / 2 fINPUT / 4 fINPUT / 8 fINPUT / 16 fINPUT / 32 fINPUT / 64 fINPUT / 128 With fINPUT=8 MHz CC2 CC1 CC0 0 0 0 8 MHz 1 0 0 4 MHz 0 1 0 2 MHz 1 1 0 1 MHz 0 0 1 500 KHz 1 0 1 250 KHz 0 1 1 125 KHz 1 1 1 62.5 KHz
Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hardware or by software. The CAR register is used to read or write the auto-reload counter "on the fly" (while it is counting).
AUTO-RELOAD REGISTER (ARR) Read /Write Reset Value: 0000 0000 (00h)
7 AR7 AR6 AR5 AR4 AR3 AR2 AR1 0 AR0
Bit 3 = TCE Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running. Bit 2 = FCRL Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. Bit 1 = OIE Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable. Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the CSR register. It indicates the transition of the counter from FFh to the ARR value. 0: New transition not yet reached 1: Transition reached
Bit 7:0 = AR[7:0] Counter Auto-Reload Data These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register has two PWM management functions: - Adjusting the PWM frequency - Setting the PWM duty cycle resolution PWM Frequency vs. Resolution:
ARR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] Resolution 8-bit > 7-bit > 6-bit > 5-bit > 4-bit fPWM Min Max ~0.244-KHz 31.25-KHz ~0.244-KHz 62.5-KHz ~0.488-KHz 125-KHz ~0.977-KHz 250-KHz ~1.953-KHz 500-KHz
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PWM AUTO-RELOAD TIMER (Cont'd) PWM CONTROL REGISTER (PWMCR) Read /Write Reset Value: 0000 0000 (00h)
7 0 0 OE1 OE0 0 0 OP1 0 OP0
DUTY CYCLE REGISTERS (DCRx) Read /Write Reset Value: 0000 0000 (00h)
7 DC7 DC6 DC5 DC4 DC3 DC2 DC1 0 DC0
Bit 7:6 = Reserved. Bit 5:4 = OE[1:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled. Bit 3:2 = Reserved. Bit 1:0 = OP[1:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the two PWM output signals.
PWMx output level Counter <= OCRx Counter > OCRx 1 0 0 1 OPx 0 1
Bit 7:0 = DC[7:0] Duty Cycle Data These bits are set and cleared by software. A DCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARR register). These DCR registers allow the duty cycle to be set independently for each PWM channel.
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
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PWM AUTO-RELOAD TIMER (Cont'd) INPUT CAPTURE CONTROL / STATUS REGISTER (ICCSR) Read /Write Reset Value: 0000 0000 (00h)
7 0 0 CS2 CS1 CIE2 CIE1 CF2 0 IC7 CF1 IC6 IC5 IC4 IC3 IC2 IC1 IC0
INPUT CAPTURE REGISTERS (ICRx) Read only Reset Value: 0000 0000 (00h)
7 0
Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x. 1: Rising edge triggers capture on channel x. Bit 3:2 = CIE[2:1] Capture Interrupt Enable These bits are set and cleared by software. They allow to enable or not the Input capture channel interrupts independently. 0: Input capture channel x interrupt disabled. 1: Input capture channel x interrupt enabled. Bit 1:0 = CF[2:1] Capture Flag These bits are set by hardware and cleared by software reading the corresponding ICRx register. Each CFx bit indicates that an input capture x has occurred. 0: No input capture on channel x. 1: An input capture has occured on channel x.
Bit 7:0 = IC[7:0] Input Capture Data These read only bits are set and cleared by hardware. An ICRx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event.
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PWM AUTO-RELOAD TIMER (Cont'd) Table 16. PWM Auto-Reload Timer Register Map and Reset Values
Address (Hex.) 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh Register Label PWMDCR1 Reset Value PWMDCR0 Reset Value PWMCR Reset Value ARTCSR Reset Value ARTCAR Reset Value ARTARR Reset Value ARTICCSR Reset Value ARTICR1 Reset Value 0 IC7 0 0 IC6 0 7 DC7 0 DC7 0 0 0 EXCL 0 CA7 0 AR7 0 6 DC6 0 DC6 0 0 0 CC2 0 CA6 0 AR6 0 5 DC5 0 DC5 0 OE1 0 CC1 0 CA5 0 AR5 0 CE2 0 IC5 0 4 DC4 0 DC4 0 OE0 0 CC0 0 CA4 0 AR4 0 CE1 0 IC4 0 3 DC3 0 DC3 0 0 0 TCE 0 CA3 0 AR3 0 CS2 0 IC3 0 2 DC2 0 DC2 0 0 0 FCRL 0 CA2 0 AR2 0 CS1 0 IC2 0 1 DC1 0 DC1 0 OP1 0 RIE 0 CA1 0 AR1 0 CF2 0 IC1 0 0 DC0 0 DC0 0 OP0 0 OVF 0 CA0 0 AR0 0 CF1 0 IC0 0
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7.7 SERIAL COMMUNICATIONS INTERFACE (SCI) 7.7.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. 7.7.2 Main Features
s s s
7.7.3 General Description The interface is externally connected to another device by two pins (see Figure 47): - TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level. - RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through this pins, serial data is transmitted and received as frames comprising: - An Idle Line prior to transmission or reception - A start bit - A data word (8 or 9 bits) least significant bit first - A Stop bit indicating that the frame is complete.
s s
s
s s
s
s
Full duplex, asynchronous communications NRZ standard format (Mark/Space) Independently programmable transmit and receive baud rates up to 250K baud. Programmable data word length (8 or 9 bits) Receive buffer full, Transmit buffer empty and End of Transmission flags Two receiver wake-up modes: - Address bit (MSB) - Idle line Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver Three error detection flags: - Overrun error - Noise error - Frame error Five interrupt sources with flags: - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error detected
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 47. SCI Block Diagram
Write
Read
(Data Register) DR
Transmit Data Register (TDR) TDO Transmit Shift Register RDI
Received Data Register (RDR)
Received Shift Register
CR1
R8 T8 M
WAKE
-
-
-
TRANSMIT CONTROL CR2
TIE TCIE RIE ILIE TE
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
SR
RE RWU SBK TDRE TC RDRF IDLE OR NF FE -
SCI INTERRUPT CONTROL
TRANSMITTER CLOCK
fCPU
Transmitter Rate Control /2 /16 /PR BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Receiver Rate Control
BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.7.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 47. It contains 4 dedicated registers: - Two control registers (CR1 & CR2) - A status register (SR) - A baud rate register (BRR) Refer to the register descriptions in Section 9.7.7 for the definitions of each bit. 7.7.4.1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the CR1 register (see Figure 47). Figure 48. Word Length Programming 9-bit Word length (M bit is set) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8
The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of "1"s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving "0"s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra "1" bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator.
Next Data Frame
Next Stop Start Bit Bit Start Bit
Idle Frame
Break Frame
Extra '1'
Start Bit
8-bit Word length (M bit is reset) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible Parity Bit Bit7 Stop Bit
Next Data Frame
Next Start Bit Start Bit Extra Start Bit '1'
Idle Frame Break Frame
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.7.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 47). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR register. - Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. - Access the SR register and write the data to send in the DR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. The following software sequence is always to clear the TDRE bit: 1. An access to the SR register 2. A write to the DR register The TDRE bit is set by hardware and it indicates that: - The TDR register is empty. - The data transfer is beginning. - The next data can be written in the DR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CC register. When a transmission is taking place, a write instruction to the DR register stores the data in the TDR register which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CC register. The following software sequence is always to clear the TC bit: 1. An access to the SR register 2. A write to the DR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 48). As long as the SBK bit is set, the SCI sends break frames to the TDO pin. After clearing this bit by software, the SCI inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, i.e. before writing the next byte in the DR.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.7.4.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the DR register consists of a buffer (RDR) between the internal bus and the received shift register (see Figure 47). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR register. - Set the RE bit to enable the receiverto begin searching for a start bit. When a character is received: - The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register. - The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SR register 2. A read to the DR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SCI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CC register. Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared. When a overrun error occurs: - The OR bit is set. - The RDR content will not be lost. - The shift register will be overwritten. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register. The OR bit is reset by an access to the SR register followed by a DR register read operation. Noise Error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. When noise is detected in a frame: - The NF is set at the rising edge of the RDRF bit. - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SR register read operation followed by a DR register read operation. Framing Error A framing error is detected when: - The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. - A break is received. When the framing error is detected: - The FE bit is set by hardware - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SR register read operation followed by a DR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.7.4.4 Baud Rate Generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU (32*PR)*TR Rx = fCPU (32*PR)*RR should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupt are inhibited. A muted receiver may be awakened by one of the following two ways: - by Idle Line detection if the WAKE bit is reset, - by Address Mark detection if the WAKE bit is set. The Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. The Receiver wakes-up by Address Mark detection when it received a "1" as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.
with: PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT0, SCT1 & SCT2 bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR0,SCR1 & SCR2 bits) All these bits are in the BRR register. Example: If fCPU is 8 MHz and if PR=13 and TR=RR=1, the transmit and receive baud rates are 19200 bauds. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. 7.7.4.5 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desirable that only the intended message recipient
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.7.5 Low Power Modes Mode WAIT HALT Description No effect on SCI. SCI interrupts exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
7.7.6 Interrupts
Interrupt Event Transmit Data Register Empty Transmission Complete Received Data Ready to be Read Overrrun Error Detected Idle Line Detected Event Flag Enable Control Bit TDRE TIE TC TCIE RDRF RIE OR IDLE ILIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruction).
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.7.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7
TDRE TC RDRF IDLE OR NF FE
Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs). This bit is not set by an idle line when the receiver wakes up from wake-up mode. 0 0 Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set the RDR register content will not be lost but the shift register will be overwritten. Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. Bit 1 = FE Framing error. This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Reserved, forced by hardware to 0.
Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if TIE =1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift register as long as the TDRE bit is not reset. Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by hardware when RE=0 or by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when an Idle Line is detected. An interrupt is generated if ILIE=1 in the CR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 0: interrupt is inhibited CONTROL REGISTER 1 (CR1) 1: An SCI interrupt is generated whenever TC=1 in Read/Write the SR register Reset Value: Undefined 7
R8 T8 0 M WAKE 0 0
0
0
Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 5 = Reserved, forced by hardware to 0. Bit 4 = M Word length. This bit determines the data length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark Bit 2:0 = Reserved, forced by hardware to 0. CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00 h) 7
TIE TCIE RIE ILIE TE RE RWU
Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SR register Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SR register. Bit 3 = TE Transmitter enable. This bit enables the transmitter and assigns the TDO pin to the alternate function. It is set and cleared by software. 0: Transmitter is disabled, the TDO pin is back to the I/O port configuration. 1: Transmitter is enabled Note: During transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble after the current word. Bit 2 = RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled, it resets the RDRF, IDLE, OR, NF and FE bits of the SR register. 1: Receiver is enabled and begins searching for a start bit. Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to "1" and then to "0", the transmitter will send a BREAK word at the end of the current word.
0
SBK
Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SR register. Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to. 7
DR7 DR6 DR5 DR4 DR3 DR2 DR1
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR dividing factor 1 2 4 8 16 32 64 128 SCT2 0 0 0 0 1 1 1 1 SCT1 0 0 1 1 0 0 1 1 SCT0 0 1 0 1 0 1 0 1
0
DR0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 47). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 47). BAUD RATE REGISTER (BRR) Read/Write Reset Value: 00xx xxxx (XXh) 7
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 & SCP0 bits, define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.
RR dividing factor 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1
0
SCR1 SCR0
Bit 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges:
PR Prescaling factor 1 3 4 13 SCP1 0 0 1 1 SCP0 0 1 0 1
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Table 17. SCI Register Map and Reset Values
Address (Hex.) 0050h 0051h 0052h 0053h 0054h Register Name SR Reset Value DR Reset Value BRR Reset Value CR1 Reset Value CR2 Reset Value 7 D7 SPIE 0 SPIF 0 D7 SPIE 0 6 D6 SPE 0 WCOL 0 D6 SPE 0 5 D5 0 0 D5 0 4 D4 MSTR 0 MODF 0 D4 MSTR 0 3 D3 CPOL x 0 D3 CPOL x 2 D2 CPHA x 0 D2 CPHA x 1 D1 SPR1 x 0 D1 SPR1 x 0 D0 SPR0 x 0 D0 SPR0 x
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7.8 SERIAL PERIPHERAL INTERFACE (SPI) 7.8.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller. Refer to the Pin Description chapter for the devicespecific pin-out. 7.8.2 Main Features s Full duplex, three-wire synchronous transfers s Master or slave operation s Four master mode frequencies s Maximum slave mode frequency = fCPU/2. s Four programmable master bit rates s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision flag protection s Master mode fault protection capability. 7.8.3 General description The SPI is connected to external devices through 4 alternate pins: - MISO: Master In Slave Out pin - MOSI: Master Out Slave In pin - SCK: Serial Clock pin - SS: Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 49. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 52) but master and slave must be programmed with the same timing mode.
Figure 49. Serial Peripheral Interface Master/Slave
MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK
SCK +5V
SS
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 50. Serial Peripheral Interface Block Diagram
Internal Bus Read Read Buffer
DR IT request
MOSI MISO
8-Bit Shift Register
SPIF WCOL - MODF -
SR
-
Write SPI STATE CONTROL
SCK SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL
SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.4 Functional Description Figure 49 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: - A Control Register (CR) - A Status Register (SR) - A Data Register (DR) Refer to the CR, SR and DR registers in Section 9.8.7for the bit definitions. 7.8.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin. Procedure - Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register). - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 52). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal).
In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is written the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 52. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 9.8.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 9.8.4.4).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge. Figure 52, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge. CPHA bit is set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. No write collision should occur even if the SS pin stays low during a transfer of several bytes (see Figure 51). CPHA bit is reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. The SS pin must be toggled high and low between each byte transmitted (see Figure 51). To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision.
Figure 51. CPHA / SS Timing Diagram
MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1)
Byte 1
Byte 2
Byte 3
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 52. Data Clock Timing Diagram
CPHA =1
SCLK (with CPOL = 1) SCLK (with CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
CPOL = 1
CPOL = 0
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.
When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision. In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must be always high on the master device. WCOL bit The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 53).
Figure 53. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SR OR
THEN
Read SR
THEN
2nd Step
Read DR
SPIF =0 WCOL=0
Write DR
SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SR
THEN
2nd Step
Read DR
WCOL=0
Note: Writing in DR register instead of reading in it do not reset WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. 7.8.4.6 Overrun Condition An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.4.7 Single Master and Multimaster Configurations For more security, the slave device may respond There are two types of SPI systems: to the master with the received data byte. Then the - Single Master System master will receive the previous byte back from the - Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR register. Single Master System Other transmission security methods can use A typical single master system may be configured, ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as mand fields. slaves (see Figure 54). Multi-master System The master device selects the individual slave deA multi-master system may also be configured by vices by using four pins of a parallel port to control the user. Transfer of master control could be imthe four SS pins of the slave devices. plemented using a handshake method through the The SS pins are pulled high during reset since the I/O ports or by an exchange of code messages master device ports will be forced to be inputs at through the serial peripheral interface system. that time, thus disabling the slave devices. The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit Note: To prevent a bus conflict on the MISO line in the SR register. the master allows only one active slave device during a transmission. Figure 54. Single Master Configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU
SS SCK Slave MCU
SS SCK Slave MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO SCK Master MCU 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.5 Low Power Modes
Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
7.8.6 Interrupts
Interrupt Event SPI End of Transfer Event Master Mode Fault Event Event Flag SPIF MODF Enable Control Bit SPIE Exit from Wait Yes Yes Exit from Halt No No
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.8.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh)
7
SPIE SPE SPR2 MSTR CPOL CPHA SPR1
0
SPR0
Bit 3 = CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1:0 = SPR[1:0] Serial peripheral rate. These bits are set and cleared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 18. Serial Peripheral Baud Rate
Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 9.8.4.5 Master Mode Fault). 0: I/O port connected to pins 1: SPI alternate functions connected to pins The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 19. 0: Divider by 2 enabled 1: Divider by 2 disabled Bit 4 = MSTR Master. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 9.8.4.5 Master Mode Fault). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
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SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h)
7 SPIF WCOL MODF 0 -
DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 53). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 9.8.4.5 Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused.
The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A write to the the DR register returns the value located in the buffer and not the contents of the shift register (See Figure 50 ).
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Table 19. SPI Register Map and Reset Values
Address (Hex.) 21 22 23 Register Name DR Reset Value CR Reset Value SR Reset Value 7 D7 SPIE 0 SPIF 0 6 D6 SPE 0 WCOL 0 5 D5 0 0 4 D4 MSTR 0 MODF 0 3 D3 CPOL x 0 2 D2 CPHA x 0 1 D1 SPR1 x 0 0 D0 SPR0 x 0
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7.9 8-BIT A/D CONVERTER (ADC) 7.9.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 7.9.2 Main Features s 8-bit conversion s Up to 16 channels with multiplexed input s Linear successive approximation s Data register (DR) which contains the results s Conversion complete status flag s On/off bit (to reduce consumption) The block diagram is shown in Figure 55. Figure 55. ADC Block Diagram 7.9.3 Functional Description 7.9.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and V SS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. See electrical characteristics section for more details.
fCPU
DIV 2
fADC
COCO
0
ADON
0
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
HOLD CONTROL
AIN1
RADC
ANALOG MUX
ANALOG TO DIGITAL CONVERTER
AINx
CADC
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
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8-BIT A/D CONVERTER (ADC) (Cont'd) 7.9.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to V DDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 7.9.3.3 A/D Conversion Phases The A/D conversion is based on two conversion phases as shown in Figure 56: s Sample capacitor loading [duration: tLOAD] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. s A/D conversion [duration: tCONV] During this phase, the A/D conversion is computed (8 successive approximations cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 7.9.3.4 Software Procedure Refer to the control/status register (CSR) and data register (DR) in Section 9.9.6 for the bit definitions and to Figure 56 for the timings. ADC Configuration The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=2/fCPU). The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH[3:0] bits to assign the analog channel to be converted. ADC Conversion In the CSR register: - Set the ADON bit to enable the A/D converter and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register and remains valid until the next conversion has ended. A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion. Figure 56. ADC Conversion Timings
ADON tCONV
ADCCSR WRITE OPERATION
HOLD CONTROL
tLOAD
COCO BIT SET
7.9.4 Low Power Modes
Mode WAIT HALT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 7.9.5 Interrupts None
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8-BIT A/D CONVERTER (ADC) (Cont'd) 7.9.6 Register Description CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h)
7
COCO 0 ADON 0 CH3 CH2 CH1
DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h)
0
CH0
7
D7 D6 D5 D4 D3 D2 D1
0
D0
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = Reserved. must always be cleared. Bit 5 = ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 = Reserved. must always be cleared. Bit 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
Channel Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bit 7:0 = D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag.
*Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
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Table 20. ADC Register Map
Address (Hex.) 0070h 0071h Register Name DR Reset Value CSR Reset Value 7 AD7 0 COCO 0 6 AD6 0 EXTCK 0 5 AD5 0 ADON 0 4 AD4 0 0 0 3 AD3 0 CH3 0 2 AD2 0 CH2 0 1 AD1 0 CH1 0 0 AD0 0 CH0 0
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8 INSTRUCTION SET
8.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do Table 21. ST7 Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination/ Source
Pointer Address (Hex.)
Pointer Size (Hex.) +0 +1
Length (Bytes)
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC-128/PC+127 00..FF 00..FF 00..FF 00..FF byte 00..FF byte
1)
+1 +2 + 0 (with X register) + 1 (with Y register) +1 +2 00..FF 00..FF 00..FF 00..FF 00..FF byte word byte word byte +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
PC-128/PC+1271)
btjt [$10],#7,skip 00..FF
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (Cont'd) 8.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
8.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 8.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 8.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
8.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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ST7 ADDRESSING MODES (Cont'd) 8.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 22. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Addition/subtraction operations Bit Compare Function
SWAP CALL, JP
Swap Nibbles Call or Jump subroutine
8.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.
Available Relative Direct/ Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC Clear
Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations
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8.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Code Condition Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION GROUPS (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) H=1? H=0? I=1? I=0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C
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INSTRUCTION GROUPS (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C <= Dst <= C C => Dst => C S = Max allowed A=A-M-C C=1 I=1 C <= Dst <= 0 C <= Dst <= 0 0 => Dst => C Dst7 => Dst => C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src H I N Z C
Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt
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9 ELECTRICAL CHARACTERISTICS
9.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to V SS. 9.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 9.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD=5V (for the 4.5VVDD5.5V voltage range) and V DD=3.3V (for the 3VVDD4V voltage range). They are given only as design guidelines and are not tested. 9.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 57. Figure 57. Pin loading conditions 9.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 58. Figure 58. Pin input voltage
ST7 PIN
VIN
ST7 PIN
CL
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9.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi9.2.1 Voltage Characteristics
Symbol VDD - VSS VIN VESD(HBM) VESD(MM) Supply voltage Input voltage on any pin 1) & 2) Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Ratings
tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Maximum value 6.5 VSS-0.3 to VDD+0.3
Unit V
see Section 9.7.2 Absolute Electrical Sensitivity
9.2.2 Current Characteristics
Symbol IVDD IVSS IIO Ratings Total current into VDD power lines (source) Total current out of VSS ground lines (sink)
3) 3)
Maximum value 80 80 25 50 - 25 5 5 5 5 pins) 5) 20
Unit
Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on ISPSEL pin IINJ(PIN) 2) & 4) Injected current on RESET pin Injected current on OSC1 and OSC2 pins Injected current on any other IINJ(PIN)
2)
mA
pin 5) & 6)
Total injected current (sum of all I/O and control
9.2.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature (see Section 10.2 THERMAL CHARACTERISTICS ) Value -65 to +150 Unit C
Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN113/152
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9.3 OPERATING CONDITIONS 9.3.1 General Operating Conditions
Symbol VDD fOSC TA Parameter Supply voltage External clock frequency Ambient temperature range Conditions see Figure 59 and Figure 60 VDD4.5V VDD3.0V Min 3.2 0 1) 0 1) -40 Max 5.5 16 8 85 Unit V MHz C
Figure 59. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for FLASH devices
fOSC [MHz] FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURE HIGHER THAN 85C 3)
FUNCTIONALITY GUARANTEED IN THIS AREA 2)
16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 8 4 1 0 2.5 3 3.2 3.5 3.85 4 4.5 5 5.5 SUPPLY VOLTAGE [V] FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1)
Notes: 1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz. 3. FLASH programming tested in production at maximum TA with two different conditions: VDD=5.5V, fCPU=8MHz and VDD=3V, fCPU=4MHz.
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OPERATING CONDITIONS (Cont'd) 9.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V DD, fOSC, and TA.
Symbol VIT+ Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) LVD voltage threshold hysteresis VDD rise time rate 3) Filtered glitch delay on VDD 2) Not detected by the LVD Conditions High Threshold Med. Threshold Low Threshold High Threshold Med. Threshold Low Threshold4) VIT+-VITMin 4.10 3.75 2) 3.25 2) 3.852) 3.502) 3.00 200 0.2
2)
Typ 1) 4.30 3.90 3.35 4.05 3.65 3.10 250
Max 4.50 4.05 3.45 4.25 3.80 3.20 300 50 40
Unit
V
VITVhyst VtPOR tg(VDD)
mV V/ms ns
Figure 60. High LVD Threshold Versus VDD and fOSC for FLASH devices 3)
fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 2.5 3 3.5 VIT-3.85 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85C FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5
Figure 61. Medium LVD Threshold Versus VDD and fOSC for FLASH devices 3)
fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 2.5 3 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85C FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5
VIT-3.5V
Figure 62. Low LVD Threshold Versus VDD and f OSC for FLASH devices 2)4)
fOSC [MHz] 16 DEVICE UNDER RESET IN THIS AREA 8 0 2.5 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85C FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 3.5 4 4.5 5 5.5
VIT-3
Notes: 1. LVD typical data are based on TA=25C. They are given only as design guidelines and are not tested. 2. Data based on characterization results, not tested in production. 3. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production. 4. If the low LVD threshold is selected, when VDD falls below 3.2V, (VDD minimum operating voltage), the device is guaranteed to continue functioning until it goes into reset state. The specified VDD min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level.
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9.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total deSymbol IDD(Ta) Parameter Supply current variation vs. temperature
vice consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
Conditions Constant VDD and fCPU Max 10 Unit %
9.4.1 RUN and SLOW Modes
Symbol Parameter 3.2VVDD3.6V 4.5VVDD5.5V Supply current in RUN mode 3) (see Figure 63) Supply current in SLOW mode 4) (see Figure 64) IDD Supply current in RUN mode 3) (see Figure 63) Supply current in SLOW mode 4) (see Figure 64) Conditions fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz Typ 1) 500 1500 5600 150 250 670 300 970 3600 100 170 420 Max 2) 900 2500 9000 450 550 1250 550 1350 4500 250 300 700 Unit
A
Figure 63. Typical IDD in RUN vs. fCPU
IDD [mA] 7 8MHz 6 5 4MHz 2MHz 500kHz
Figure 64. Typical IDD in SLOW vs. fCPU
IDD [mA] 0.8 0.7 0.6 0.5 500kHz 250kHz 125kHz 31.25kHz
4
0.4
3
0.3
2 1 0 3.2 3.5 4 4.5 5 5.5 VDD [V]
0.2 0.1 0 3.2 3.5 4 4.5 5 5.5 VDD [V]
Notes: 1. Typical data are based on TA=25C, VDD=5V (4.5VVDD5.5V range) and VDD=3.4V (3.2VVDD3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. CPU running with memory access, all I/O pins in output mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 9.4.2 WAIT and SLOW WAIT Modes
Symbol Parameter 3.2VVDD3.6V 4.5VVDD5.5V Supply current in WAIT mode 3) (see Figure 65) Supply current in SLOW WAIT mode 4) (see Figure 66) IDD Supply current in WAIT mode 3) (see Figure 65) Supply current in SLOW WAIT mode 4) (see Figure 66) Conditions fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz Typ 1) 150 560 2200 20 90 340 90 350 1370 10 50 200 Max 2) 280 900 3000 70 190 850 200 550 1900 20 80 350 Unit
A
Figure 65. Typical IDD in WAIT vs. f CPU
IDD [mA] 3 8MHz 2.5 4MHz 2MHz 500kHz
Figure 66. Typical IDD in SLOW-WAIT vs. fCPU
IDD [mA] 0.35 0.3 0.25 500kHz 250kHz 125kHz 31.25kHz
2 0.2 1.5 0.15 1 0.1 0.5 0.05 0 3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5 VDD [V] VDD [V]
0
Notes: 1. Typical data are based on TA=25C, VDD=5V (4.5VVDD5.5V range) and VDD=3.4V (3.2VVDD3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. All I/O pins in output mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 9.4.3 HALT Mode
Symbol IDD Parameter Supply current in HALT mode 2) VDD=5.5V VDD=3.6V Conditions -40CTA+85C -40CTA+85C Typ 1) 0 Max 10 6 Unit A
9.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock
Symbol Parameter Supply current of internal RC oscillator Supply current of external RC oscillator 4) IDD(CK)
source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Conditions Typ 1) 500 525 200 300 450 700 150 HALT mode 100 Max 3) 750 750 400 550 750 1000 350 150 A Unit
LP: Low power oscillator MP: Medium power oscillator Supply current of resonator oscillator 4) & 5) MS: Medium speed oscillator HS: High speed oscillator Clock security system supply current
IDD(LVD)
LVD supply current
9.4.5 On-Chip Peripherals
Symbol IDD(TIM) IDD(SPI) IDD(I2C) IDD(ADC) Parameter 16-bit Timer supply current 6) SPI supply current 7) I C supply current
2 8)
Conditions fCPU=8MHz fCPU=8MHz fCPU=8MHz fADC=4MHz VDD=3.4V VDD=5.0V VDD=3.4V VDD=5.0V VDD=3.4V VDD=5.0V VDD=3.4V VDD=5.0V
Typ 50 150 250 350 250 350 800 1100
Unit
A
ADC supply current when converting 9)
Notes: 1. Typical data are based on TA=25C. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), CSS and LVD disabled. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. Data based on characterization results, not tested in production. 4. Data based on characterization results done with the external components specified in Section 9.5.3 and Section 9.5.4, not tested in production. 5. As the oscillator is based on a current source, the consumption does not depend on the voltage. 6. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer counter stopped (selecting external clock capability). Data valid for one timer. 7. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communication (data sent equal to 55h). 8. Data based on a differential IDD measurement between reset configuration and I2C peripheral enabled (PE bit set). 9. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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9.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA. 9.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
2)
Conditions fCPU=8MHz fCPU=8MHz
Min 2 250 10 1.25
Typ 1) 3 375
Max 12 1500 22 2.75
Unit tCPU ns tCPU s
9.5.2 External Clock Source
Symbol VOSC1H VOSC1L tw(OSC1H) tw(OSC1L) tr(OSC1) tf(OSC1) IL Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 3) OSC1 rise or fall time 3) OSCx Input leakage current VSSVINVDD see Figure 67 Conditions Min 0.7xVDD VSS 15 ns 15 1 A Typ Max VDD 0.3xVDD Unit V
Figure 67. Typical Application with an External Clock Source
90% VOSC1H 10%
VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
OSC2 Not connected internally fOSC EXTERNAL CLOCK SOURCE OSC1 IL ST72XXX
Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production.
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) 9.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external componants. In the application, the resonator and the load capacitors have to be placed as
Symbol fOSC RF CL1 CL2 Parameter Oscillator Frequency 3) Feedback resistor
close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Conditions Min 1 >2 >4 >8 20 LP oscillator MP oscillator MS oscillator HS oscillator LP oscillator MP oscillator MS oscillator HS oscillator 38 32 18 15 40 50 100 250 Max 2 4 8 16 40 56 46 26 21 130 300 550 820 Unit MHz k pF
LP: Low power oscillator MP: Medium power oscillator MS: Medium speed oscillator HS: High speed oscillator
RS=200 Recommanded load capacitances verRS=200 sus equivalent serial resistance of the RS=200 crystal or ceramic resonator (RS) RS=100 OSC2 driving current VDD=5V VIN=VSS
i2
A
Oscil. LP JAUCH Crystal MP MS HS LP MP MS HS
Typical Crystal or Ceramic Resonators Reference S-200-30-30/50 SS3-400-30-30/30 SS3-800-30-30/30 SS3-1600-30-30/30 CSA2.00MG CSA4.00MG CSA8.00MTZ CSA16.00MXZ040 Freq. Characteristic 1) 2MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=200 4MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=60
CL1 CL2 tSU(osc) [pF] [pF] [ms] 2) 33 33 34 34 34 34 30 30 30 30 10~15 7~10 2.5~3 1~1.5 4.2 2.1 1.1 0.7
MURATA
Ceramic
8MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=25 33 16MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=15 33 2MHz fOSC=[0.5%tolerance,0.3%Ta,0.3%aging,x.x%correl] 33 4MHz fOSC=[0.5%tolerance,0.3%Ta,0.3%aging,x.x%correl] 33 8MHz fOSC=[0.5%tolerance,0.5%Ta,0.3%aging,x.x%correl] 33 16MHz fOSC=[0.5%tolerance,0.3%Ta,0.3%aging,x.x%correl] 33
Figure 68. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH INTEGRATED CAPACITORS
i2
fOSC OSC1
CL1
RESONATOR CL2 OSC2
RF ST72XXX
Notes: 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a quick VDD ramp-up from 0 to 5V (<50s). 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details.
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CLOCK CHARACTERISTICS (Cont'd) 9.5.4 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal
Symbol fOSC Parameter Internal RC oscillator frequency
1)
or external components (selectable by option byte).
Conditions Min 3.60 1 2.0 Typ Max 5.10 14 1.0 6.5 0.7 3.0 10 0 5) 47 470 Unit MHz
see Figure 69
External RC oscillator frequency 2) Internal RC Oscillator Start-up Time 3) REX=47K, CEX="0"pF REX=47K, CEX=100pF REX=10K, CEX=6.8pF REX=10K, CEX=470pF see Figure 70
tSU(OSC)
External RC Oscillator Start-up Time Oscillator external resistor 4) Oscillator external capacitor
3)
ms
REX CEX
K pF
Figure 69. Typical Application with RC oscillator
ST72XXX
INTERNAL RC VDD
Current copy
EXTERNAL RC REX OSC1
VREF
+ -
fOSC
CEX
OSC2
Voltage generator
CEX discharge
Figure 70. Typical Internal RC Oscillator
fosc [MHz] 4.25 4.2 4.15 4.1 4.05 4 3.95 3.9 3.85 3.2 VDD [V] 5.5 -40C +25C +85C
Figure 71. Typical External RC Oscillator
fosc [MHz] 20 15 10 5 0 0 6.8 22 47 Cex [pF] 100 270 470 Rex=10KOhm Rex=15KOhm Rex=22KOhm Rex=33KOhm Rex=39KOhm Rex=47KOhm
Notes: 1. Data based on characterization results. 2. Guaranteed frequency range with the specified CEX and REX ranges taking into account the device process variation. Data based on design simulation. 3. Data based on characterization results done with VDD nominal at 5V, not tested in production. 4. REX must have a positive temperature coefficient (ppm/C), carbon resistors should therefore not be used. 5. Important: when no external CEX is applied, the capacitance to be considered is the global parasitic capacitance which is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by trying out several resistor values.
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CLOCK CHARACTERISTICS (Cont'd) 9.5.5 Clock Security System (CSS)
Symbol fSFOSC fGFOSC Parameter Safe Oscillator Frequency 1) Glitch Filtered Frequency 2) Conditions TA=25C, VDD=5.0V TA=25C, VDD=3.4V Min 250 190 Typ 340 260 30 Max 430 330 Unit kHz MHz
Figure 72. Typical Safe Oscillator Frequencies
fosc [kHz] 400 350 300 -40C +25C +85C
250 200 3.2 VDD [V] 5.5
Note: 1. Data based on characterization results, tested in production between 90KHz and 500KHz. 2. Filtered glitch on the fOSC signal. See functional description in section 4.3 on page 21 for more details.
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9.6 MEMORY CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. 9.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode 1) Conditions HALT mode (or RESET) Min 1.6 Typ Max Unit V
9.6.2 FLASH Program Memory
Symbol TA(prog) tprog tret NRW Parameter Programming temperature range
2)
Conditions
Min 0
Typ 25 8 2.1
Max 70 25 6.4
Unit C ms sec years cycles
Programming time for 1~16 bytes 3) TA=+25C Programming time for 4 or 8kBytes TA=+25C Data retention 5) TA=+55C TA=+25C
4)
20 100
Write erase cycles 5)
Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Data based on characterization results, tested in production at TA=25C. 3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device) 4. The data retention time increases when the TA decreases. 5. Data based on reliability test results and monitored in production.
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9.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 9.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). - ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. - FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed.
Conditions VDD=5V, TA=+25C, fOSC=8MHz conforms to IEC 1000-4-2 Neg 1) -1 -4 Pos 1) 1 kV 4 Unit
Symbol VFESD VFFTB
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be apVDD=5V, TA=+25C, fOSC=8MHz plied through 100pF on VDD and VDD pins conforms to IEC 1000-4-4 to induce a functional disturbance
Figure 73. EMC Recommended star network power supply connection 2)
ST72XXX 10nF 0.1F
ST7 DIGITAL NOISE FILTERING
VDD
VSS
VDD
POWER SUPPLY SOURCE
VSSA
EXTERNAL NOISE FILTERING
VDDA 0.1F
Notes: 1. Data based on characterization results, not tested in production. 2. The suggested 10nF and 0.1F decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
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EMC CHARACTERISTICS (Cont'd) 9.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note. 9.7.2.1 Electro-Static Discharge (ESD) Electro-Static Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). Two models are usually simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. See Figure 74 and the following test sequences. Human Body Model Test Sequence - C L is loaded through S1 by the HV pulse generator. - S1 switches position from generator to R. - A discharge from CL through R (body resistance) to the ST7 occurs. - S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse. Absolute Maximum Ratings
Symbol VESD(HBM) VESD(MM) Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)
Machine Model Test Sequence - CL is loaded through S1 by the HV pulse generator. - S1 switches position from generator to ST7. - A discharge from CL to the ST7 occurs. - S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse. - R (machine resistance), in series with S2, ensures a slow discharge of the ST7.
Conditions TA=+25C TA=+25C
Maximum value 1) Unit 2000 V 200
Figure 74. Typical Equivalent ESD Circuits
S1 R=1500 S1
R=10k~10M
HIGH VOLTAGE PULSE GENERATOR
CL=100pF
ST7
S2
HIGH VOLTAGE PULSE GENERATOR CL=200pF
ST7
S2
HUMAN BODY MODEL
MACHINE MODEL
Notes: 1. Data based on characterization results, not tested in production.
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EMC CHARACTERISTICS (Cont'd) 9.7.2.2 Static and Dynamic Latch-Up - LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the AN1181 ST7 application note. Electrical Sensitivities
Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class
- DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards and is described in Figure 75. For more details, refer to the AN1181 ST7 application note.
Conditions TA=+25C TA=+85C VDD=5.5V, fOSC=4MHz, TA=+25C
Class 1) A A A
Figure 75. Simplified Diagram of the ESD Generator for DLU
RCH=50M RD=330
DISCHARGE TIP
VDD VSS
CS=150pF ESD GENERATOR 2)
HV RELAY
ST7
DISCHARGE RETURN CONNECTION
Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger.
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EMC CHARACTERISTICS (Cont'd) 9.7.3 ESD Pin Protection Strategy To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be protected must not receive excessive current, voltage or heating within their structure. An ESD network combines the different input and output ESD protections. This network works, by allowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 76 and Figure 77 for standard pins and in Figure 78 and Figure 79 for true open drain pins.
Standard Pin Protection To protect the output structure the following elements are added: - A diode to VDD (3a) and a diode from VSS (3b) - A protection device between VDD and V SS (4) To protect the input structure the following elements are added: - A resistor in series with the pad (1) - A diode to VDD (2a) and a diode from VSS (2b) - A protection device between VDD and V SS (4)
Figure 76. Positive Stress on a Standard Pad vs. VSS
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path Path to avoid
(3b) (2b)
VSS
VSS
Figure 77. Negative Stress on a Standard Pad vs. VDD
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path
(3b) (2b)
VSS
VSS
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EMC CHARACTERISTICS (Cont'd) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to V DD are not implemented. An additional local protection between the pad and V SS (5a & 5b) is implemented to completly absorb the positive ESD discharge. Multisupply Configuration When several types of ground (VSS, V SSA, ...) and power supply (VDD, VDDA, ...) are available for any reason (better noise immunity...), the structure shown in Figure 80 is implemented to protect the device against ESD.
Figure 78. Positive Stress on a True Open Drain Pad vs. VSS
VDD VDD
Main path Path to avoid
(1) OUT (4) IN
(5a)
(3b)
(2b)
(5b)
VSS
VSS
Figure 79. Negative Stress on a True Open Drain Pad vs. VDD
VDD VDD
Main path
(1) OUT (4) IN
(3b)
(3b)
(2b)
(3b)
VSS
VSS
Figure 80. Multisupply Configuration
VDD VDDA
VDDA
VSS
BACK TO BACK DIODE BETWEEN GROUNDS
VSSA
VSSA
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9.8 I/O PORT PIN CHARACTERISTICS 9.8.1 General Characteristics Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys IL IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Parameter Input low level voltage
2)
Conditions
Min 0.7xVDD
Typ 1)
Max 0.3xVDD
Unit V mV
Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Input leakage current Static current consumption 4) Weak pull-up equivalent resistor 5) I/O pin capacitance Output high to low level fall time 6) External interrupt pulse time 7) CL=50pF Output low to high level rise time 6) Between 10% and 90% VSSVINVDD Floating input mode VIN=VSS VDD=5V VDD=3.3V
400 1 200 70 170 120 200 5 25 25 1 250 230
A k pF ns tCPU
Figure 81. Two typical Applications with unused I/O Pin
VDD 10k
ST72XXX
10k UNUSED I/O PORT UNUSED I/O PORT
ST72XXX
Figure 82. Typical IPU vs. VDD with V IN=VSS
Ipu [A] 70 60 50 40 30 20 10 0 3.2 3.5 4 Vdd [V] 4.5 5 5.5 Ta=-40C Ta=25C Ta=85C
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 81). Data based on design simulation and/or technology characteristics, not tested in production. 5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 82). This data is based on characterization results, tested in production at VDD max. 6. Data based on characterization results, not tested in production. 7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
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I/O PORT PIN CHARACTERISTICS (Cont'd) 9.8.2 Output Driving Current Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 83 and Figure 86) VDD=5V Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 85 and Figure 87) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 86 and Figure 88) Conditions IIO=+5mA IIO=+2mA IIO=+20mA IIO=+8mA IIO=-5mA IIO=-2mA VDD-1.8 VDD-0.7 Min Max 1.2 0.5 1.5 0.6 V Unit
VOL 1)
VOH 2)
Figure 83. Typical VOL at VDD=5V (standard)
Vol [V] at Vdd=5V 2 Ta=-40C 1.5 1 0.5 0 0 2 4 Iio [mA] 6 8 10 Ta=25C Ta=85C
Figure 85. Typical VDD-VOH at VDD=5V
Vdd-Voh [V] at Vdd=5V 5.5 5 4.5 4 3.5 3 2.5 2 -8 -6 -4 Iio [mA] -2 0 Ta=-40C Ta=25C Ta=85C
Figure 84. Typical VOL at VDD=5V (high-sink)
Vol [V] at Vdd=5V 1.5 Ta=-40C 1 Ta=25C Ta=85C
0.5
0 0 5 10 15 Iio [mA] 20 25 30
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 9.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 9.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 86. Typical VOL vs. VDD (standard I/Os)
Vol [V] at Iio=2mA 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 4.5 5 5.5 Vdd [V] Ta=-40C Ta=25C Ta=85C Vol [V] at Iio=5mA 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 3.2 3.5 Ta=-40C Ta=25C Ta=85C
4
4.5
5
5.5
Vdd [V]
Figure 87. Typical VOL vs. VDD (high-sink I/Os)
Vol [V] at Iio=8mA 0.5 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 4.5 5 5.5 Vdd [V] Ta=-40C Ta=25C Ta=85C Vol [V] at Iio=20mA Ta=-40C 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 3.2 3.5 4 4.5 5 5.5 Vdd [V]
Ta=25C
Ta=85C
Figure 88. Typical VDD-VOH vs. VDD
Vdd-Voh [V] at Iio=-2mA 5.5 5 4.5 4 3.5 3 2.5 2 3.2 3.5 4 4.5 5 5.5 Vdd [V] Ta=25C 1 0 3.5 4 4.5 Vdd [V] 5 5.5 Ta=-40C Ta=85C 3 2 Ta=-40C Ta=25C Ta=85C Vdd-Voh [V] at Iio=-5mA 5 4
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9.9 CONTROL PIN CHARACTERISTICS 9.9.1 Asynchronous RESET Pin Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys VOL RON Parameter Input low level voltage
2)
Conditions
Min 0.7xVDD
Typ 1)
Max 0.3xVDD
Unit V mV
Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Output low level voltage (see Figure 91, Figure 92) Weak pull-up equivalent resistor 5)
4)
400 VDD=5V VIN=VSS IIO=+5mA IIO=+2mA VDD=5V VDD=3.4V 20 80 0.68 0.28 40 100 6 30 20 100 0.95 0.45 60 120
V k 1/fSFOSC s s ns
tw(RSTL)out Generated reset pulse duration th(RSTL)in External reset pulse hold time 6) tg(RSTL)in Filtered glitch duration 7)
External pin or internal reset sources
Figure 89. Typical Application with RESET pin 8)
VDD
NA
L
ST72XXX
PT
IO
VDD
VDD RON
USER EXTERNAL RESET CIRCUIT 8)
0.1F
4.7k RESET
INTERNAL RESET CONTROL
O
0.1F
WATCHDOG RESET LVD RESET
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The IIO current sunk must always respect the absolute maximum rating specified in Section 9.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics described in Figure 90). This data is based on characterization results, not tested in production. 5. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. 6. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored. 7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy environment. 8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
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CONTROL PIN CHARACTERISTICS (Cont'd) Figure 90. Typical ION vs. VDD with VIN=VSS
Ion [A] 200 Ta=-40C 150 100 Ta=25C Ta=85C
Figure 91. Typical VOL at VDD=5V (RESET)
Vol [V] at Vdd=5V 1.5 Ta=25C 1 Ta=-40C Ta=85C
0.5
50 0 3.2 3.5 4 4.5 5 5.5 Vdd [V]
0 0 1 2 3 4 Iio [mA] 5 6 7 8
Figure 92. Typical VOL vs. VDD (RESET)
Vol [V] at Iio=2mA 0.45 0.4 0.35 0.3 0.25 0.2 0.15 3.2 3.5 4 4.5 5 5.5 Vdd [V] Ta=25C Ta=-40C Ta=85C
Vol [V] at Iio=5mA 1.2 1 0.8 0.6 0.4 3.2 3.5 4
Ta=-40C Ta=25C
Ta=85C
4.5
5
5.5
Vdd [V]
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CONTROL PIN CHARACTERISTICS (Cont'd) 9.9.2 ISPSEL Pin Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH IL Parameter Input low level voltage 1) Input high level voltage 1) Input leakage current VIN=VSS Conditions Min VSS VDD-0.1 Max 0.2 12.6 1 Unit
V
A
Figure 93. Two typical Applications with ISPSEL Pin 2)
ISPSEL
PROGRAMMING TOOL 10k
ISPSEL
ST72XXX
ST72XXX
Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. 2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to VSS.
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9.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).
9.10.1 Watchdog Timer
Symbol tw(WDG) Parameter Watchdog time-out duration Conditions Min 12,288 fCPU=8MHz 1.54 Typ Max 786,432 98.3 Unit tCPU ms
9.10.2 8-Bit PWM Auto-reload Timer
Symbol Parameter Conditions Min 1 1 fCPU=8MHz 125 0 0 fCPU/2 fCPU/2 8 Typ Max Unit tCPU tCPU ns MHz MHz bit
tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fEXT fPWM Timer external clock frequency PWM repetition rate
ResPWM PWM resolution
9.10.3 16-Bit Timer
Symbol Parameter Conditions Min 1 2 fCPU=8MHz 250 0 0 fCPU/4 fCPU/4 16 Typ Max Unit tCPU tCPU ns MHz MHz bit
tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fEXT fPWM Timer external clock frequency PWM repetition rate
ResPWM PWM resolution
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9.11 COMMUNICATION INTERFACE CHARACTERISTICS 9.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter Master SPI clock frequency fCPU=8MHz Slave fCPU=8MHz SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge) 0 0.25 0.25 tCPU
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Conditions Min fCPU/128 0.0625 0 Max fCPU/4 2 fCPU/2 4 Unit
MHz
see I/O port pin description 120 120 100 90 100 100 100 100 0 120 240 120
ns
Figure 94. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
see note 2
see note 2
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 95. SPI Slave Timing Diagram with CPHA=11)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
MISO OUTPUT
see note 2
HZ
MSB OUT
BIT6 OUT
see note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 96. SPI Master Timing Diagram 1)
SS INPUT tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont'd) 9.11.2 SCI - Serial Communications Interface Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter fCPU Accuracy vs. Standard
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO).
Conditions Prescaler Conventional Mode TR (or RR)=64, PR=13 TR (or RR)=16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 2, PR=13 TR (or RR)= 8, PR= 3 TR (or RR)= 1, PR=13 Extended Mode ETPR (or ERPR) = 13 Standard Baud Rate Unit
fTx fRx
~0.16% Communication frequency 8MHz
~300.48 300 1200 ~1201.92 2400 ~2403.84 4800 ~4807.69 9600 ~9615.38 10400 ~10416.67 19200 ~19230.77 38400 ~38461.54 14400 ~14285.71
Hz
~0.79%
Extended Mode ETPR (or ERPR) = 35
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9.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol fADC VAIN RAIN CADC tSTAB tADC Parameter ADC clock frequency Conversion range voltage External input resistor Internal sample and hold capacitor Stabilization time after ADC enable Conversion time (Sample+Hold) - Sample capacitor loading time - Hold conversion time fCPU=8MHz, fADC=4MHz 6 0
4) 2)
Conditions
Min VSSA
Typ 1)
Max 4 VDDA 10
3)
Unit MHz V k pF s 1/fADC
3 4 8
Figure 97. Typical Application with ADC
VDD VT 0.6V RAIN VAIN CIO ~2pF VDD VDDA VT 0.6V IL 1A AINx
ADC
0.1F VSSA
ST72XXX
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V. They are given only as design guidelines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS . 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid.
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8-BIT ADC CHARACTERISTICS (Cont'd) ADC Accuracy
Symbol |ET| EO EG |ED| |EL| Parameter Total unadjusted error 1) Offset error 1) Gain Error 1) Differential linearity Integral linearity error 1) error 1) VDD=5.0V, 3) fCPU=8MHz -0.5 -0.5 Conditions Min Max 1 0.5 0.5 0.5 0.5 LSB Unit
Figure 98. ADC Accuracy Characteristics
Digital Result ADCDR 255 254 253 1LSB IDE AL V -V DDA SSA = ---------------------------------------256 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL Vin (LSBIDEAL) 5 6 7 253 254 255 256 VDDA EO EL ED (3) (1) EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Notes: 1. ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB for each 10K increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. 3. Data based on characterization results over the whole temperature range, monitored in production.
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9.13 OP-AMP Module Characteristics These op-amp specific values take precedence over any generic values given elsewhere in the document. (T =25oC, VDD - VSS = 5 V ). SPGA1 / SPGA2 - Software Programmable Gain Operational Amplifiers Symbol
|Vio| ICC CMR 3) SVR 3) Avd 3) VOH VOL ISC 3) GPB SR
+
Parameter
Input Offset Voltage Supply Current per amplifier 2) Common Mode Rejection Ratio Supply Voltage Rejection Ratio Voltage Gain High Level Ouput Voltage Low Level Ouput Voltage Short circuit Current Sourced Short circuit Current Sunk Gain Bandwidth Product Slew Rate
5)
Condition
Min
Typ
3
Max
10 2
Unit
mV mA dB dB V/mV V
VDD=5.0V, AVCL=1, no load1) 70 70 (RL=1K) (RL=10K) VDD=5V (RL=10K) VDD=5V Vo= 5V connected to VSS Vo= 0V connected to VDD 45 70 100 4.9
0.8
0.10
V mA mA
4 AVCL=1
1)
MHz V/s V/s 50 nV Hz- 1 Degrees pF VDD +0.2 10 10 10 V % % %
1 1
SRen 3) m 3) Cin 4) Vicm 4) VRef VBG Gain
Slew Rate 5) Thermal Noise Phase margin Input Capacitance Common Mode Input Voltage Range Reference Voltage (VDDA/8 step) Precision Band Gap Precision Programmable Gain Precision
AVCL=11)
40
55 10
VSS0.2
1) A VCL = Closed loop gain (repeater configuration) 2) Tested with positve input connected to internal band gap (reference voltage enabled) and negative input floating. 3) Data based on characterization, not tested in production 4) Data guaranteed by design, not tested in production 5) Slew rate is the rate of change from 10% to 90% of the output voltage step.
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OP-AMP MODULE CHARACTERISTICS (Cont'd) OA3 Operational Amplifier Symbol
|Vio|
Parameter
Input Offset Voltage
Condition
Min
Typ
3
Max
10
Unit
mV
ICC CMR 2) SVR
2)
Supply Current per amplifier
VDD=5.0V, AVCL=1, no load1)
300
500
A
Common Mode Rejection Ratio Supply Voltage Rejection Ratio Voltage Gain High Level Ouput Voltage Low Level Ouput Voltage Short circuit Current Sourced Short circuit Current Sunk Gain Bandwidth Product Slew Rate4) Slew Rate
4)
70 70 (RL=1K) (RL=10K) VDDA=5V (RL=10K) VDDA=5V Vo= 1 connected to VSS Vo= 0 connected to VDD 45 70 6 AVCL=11) AVCL=1
1)
dB dB V/mV V 0.10 V mA mA MHz V/s V/s 50 nV Hz- 1 Degrees pF VDD +0.2 V
Avd 2) VOH VOL ISC 2) GPB SR+ SR
-
100 4.9
1 1
en 2) m 2) Cin 3) Vicm 3)
Thermal Noise Phase margin Input Capacitance Common Mode Input Voltage Range VSS0.2 40 55 10
1) A VCL = Closed loop gain (repeater configuration) 2) Data based on characterization, not tested in production 3) Data guaranteed by design, not tested in production 4) Slew rate is the rate of change from 10% to 90% of the output voltage step.
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9.13.1 Typical Phase Gain vs. Frequency Figure 99. Gain vs Frequency
60
180 150
40
120 90 Phase (Deg)
Gain (dB)
20
60 30
0
0 -30
-20
-60 -90
-40 1.00E+3 1.00E+4 1.00E+5 1.00E+6
-120 1.00E+7 Gain (dB) Phase (Deg)
load RL=2Kohm CL= 120pF VDD=5V
9.13.2 Typical Total Harmonic Distorsion Figure 100 shows three typical curves for different VDD values. This characterisation has been done at TA 25C using a 1 kHz sine wave signal with an Figure 100. Total Harmonic Distorsion vs Vout
0.2
average value of VDD/2. This signal is input to the SPGA configured in non-inverter mode with a gain of 1. The SPGA output is loaded with a 1K resistor.
0.15
Distorsion(%)
0.1
Vdd=6V Vdd=5V Vdd=3V
0.05
0 0 1 2 3 4 5 6 7
VOUT peak-peak (V)
RL =10Kohm, F= 1KHz
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10 GENERAL INFORMATION
10.1 PACKAGE MECHANICAL DATA Figure 101. 32-Pin Shrink Plastic Dual In Line Package
mm Min 0.51 3.05 3.56 0.36 0.46 0.76 1.02 0.20 0.25 Typ Max Min 0.020 4.57 0.120 0.140 0.180 0.58 0.014 0.018 0.023 1.40 0.030 0.040 0.055 0.36 0.008 0.010 0.014 3.56 3.76 inches Typ Max 5.08 0.140 0.148 0.200
E See Lead Detail
Dim. A A1 A2
C
b
b1
b e3 D
eA eB
b1 C D E E1
27.43 27.94 28.45 1.080 1.100 1.120 9.91 10.41 11.05 0.390 0.410 0.435 7.62 8.89 1.78 10.16 12.70 2.54 3.05 Number of Pins 9.40 0.300 0.350 0.370 0.070 0.400 0.500 3.81 0.100 0.120 0.150 32
N E1 e 1 N/2
A2 A A1 L
e eA eB L
VR01725J
N
Figure 102. 34-Pin Small Outline
Dim. A A1 B 0.10mm .004 seating plane C D E e H h K L N SO34S
mm Min 2.46 0.13 0.36 0.23 17.73 7.42 1.02 10.16 0.64 0.61 10.41 0.400 0.74 0.025 0 1.02 0.024 Typ Max Min 2.64 0.097 0.29 0.005 0.48 0.014 0.32 0.0091 18.06 0.698 7.59 0.292
inches Typ Max 0.104 0.0115 0.019 0.0125 0.711 0.299 0.040 0.410 0.029 8 0.040
Number of Pins 34
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10.2 THERMAL CHARACTERISTICS
Symbol RthJA PD TJmax Ratings Package thermal resistance (junction to ambient) SDIP32 SO34 Power dissipation 1) Maximum junction temperature
2)
Value 60 70 500 150
Unit C/W mW C
Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
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10.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 103 and Figure 104. Recommended glue for SMD plastic packages dedicated to molding compound with silicone: s Heraeus: PD945, PD955 s Loctite: 3615, 3298
Figure 103. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250 200 150 Temp. [C] 100 50 0 20 40 60 80 100 120 140 160 PREHEATING PHASE Time [sec] 80C 5 sec SOLDERING PHASE COOLING PHASE (ROOM TEMPERATURE)
Figure 104. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250 200 150 Temp. [C] 100 50 0 100 200 300 400
ramp up 2C/sec for 50sec ramp down natural 2C/sec max 90 sec at 125C 150 sec above 183C Tmax=220+/-5C for 25 sec
Time [sec]
10.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 23. Suggested List of SDIP32 Socket Types
Package / Probe SDIP32 EMU PROBE TEXTOOL Adaptor / Socket Reference 232-1291-00 Same Footprint X Socket Type Textool
Table 24. Suggested List of SO34 Socket Types
Package / Probe SO34 EMU PROBE Adaptor / Socket Reference Emulator Probe includes an adapter with S034 footprint to be soldered on user PCB Same Footprint X Socket Type N/A
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11 DEVICE CONFIGURATION AND ORDERING INFORMATION
The device is available for production a user programmable version (FLASH). FLASH devices are shipped to customers with a default content (FFh). FLASH devices have to be configured by the customer using the Option Bytes. 11.1 OPTION BYTES The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). USER OPTION BYTE 0 Bit 7:1 = Reserved, must always be 1. Bit 1= OA3E Op-Amp 3 Enable This option bit enables or disables the third OpAmp of the on-chip Op-Amp Module. 0: OE3 disabled 1: OE3 enabled Bit 0 = FMP Full memory protection. This option bit enables or disables external access to the internal program memory (read-out protection). Clearing this bit causes the erasing (to 00h) of the whole memory (including the option byte). 0: Program memory not read-out protected 1: Program memory read-out protected USER OPTION BYTE 1 Bit 7 = CFC Clock filter control on/off This option bit enables or disables the clock filter (CF) features.
0: Clock filter enabled 1: Clock filter disabled Bit 6:4 = OSC[2:0] Oscillator selection These three option bits can be used to select the main oscillator as shown in Table 25. Bit 3:2 = LVD[1:0] Low voltage detection selection These option bits enable the LVD block with a selected threshold as shown in Table 26. Bit 1 = WDG HALT Watchdog and halt mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Bit 0 = WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) Table 25. Main Oscillator Configuration
Selected Oscillator External Clock (Stand-by) ~4 MHz Internal RC 1~14 MHz External RC Low Power Resonator (LP) Medium Power Resonator (MP) Medium Speed Resonator (MS) High Speed Resonator (HS) OSC2 OSC1 OSC0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 X 1 0 1 0
Table 26. LVD Threshold Configuration
Configuration LVD Off Highest Voltage Threshold (4.50V) Medium Voltage Threshold (4.05V) Lowest Voltage Threshold (3.45V) LVD1 LVD0 1 1 0 0 1 0 1 0
USER OPTION BYTE 0 7 Reserved Default Value 1 1 1 1 1 1 0 OA3E FMP 1 0 7 CFC 1
USER OPTION BYTE 1 0 OSC OSC OSC WDG WDG LVD1 LVD0 2 1 0 HALT SW 1 1 0 1 1 1 1
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11.2 DEVICE ORDERING INFORMATION Figure 105. FLASH User Programmable Device Type
TEMP. DEVICE PACKAGE RANGE 6= industrial -40 to +85 C
B= Plastic DIP M= Plastic SOIC ST72C171K2
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11.3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: http//mcu.st.com. Third Party Tools s ACTUM s BP s COSMIC s CMX s DATA I/O s HITEX s HIWARE s ISYSTEM s KANDA s LEAP Tools from these manufacturers include C compliers, emulators and gang programmers. Table 27. STMicroelectronic Tool Features
In-Circuit Emulation ST7 HDS2 Emulator Yes, powerful emulation features including trace/ logic analyzer Programming Capability1) No Software Included ST7 CD ROM with: - ST7 Assembly toolchain - STVD7 and WGDB7 powerful Source Level Debugger for Win 3.1, Win 95 and NT - C compiler demo versions Yes (All packages),support - ST Realizer for Win 3.1 and Win also ISP 1) 95. - Windows Programming Tools for Win 3.1, Win 95 and NT
STMicroelectronics Tools Two types of development tool are offered by ST, all of them connect to a PC via a parallel (LPT) port: see Table 27 and Table 28 for more details.
ST7 Programming Board No
Table 28. Dedicated STMicroelectronics Development Tools
Supported Product ST72C171K2, ST7 HDS2 Emulator ST7MDT6-EMU2B ST7 Programming Board ST7MDT6-EPB2/EU ST7MDT6-EPB2/US ST7MDT6-EPB2/UK
Note: 1. In-Situ Programming (ISP) interface for FLASH devices.
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ST72C171
11.4 ST7 APPLICATION NOTES
IDENTIFICATION DESCRIPTION PROGRAMMING AND TOOLS AN985 EXECUTING CODE IN ST7 RAM AN986 USING THE ST7 INDIRECT ADDRESSING MODE AN987 ST7 IN-CIRCUIT PROGRAMMING AN988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN989 STARTING WITH ST7 HIWARE C AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 EXAMPLE DRIVERS AN969 ST7 SCI COMMUNICATION BETWEEN THE ST7 AND A PC AN970 ST7 SPI COMMUNICATION BETWEEN THE ST7 AND EPROM AN971 ST7 IC COMMUNICATION BETWEEN THE ST7 AND EPROM AN972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN974 REAL TIME CLOCK WITH THE ST7 TIMER OUTPUT COMPARE AN976 DRIVING A BUZZER USING THE ST7 PWM FUNCTION AN979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 USB MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR IC SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 SOFTWARE IMPLEMENTATION OF IC BUS MASTER AN1046 ST7 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERAL AN1048 ST7 SOFTWARE LCD DRIVER AN1078 ST7 TIMER PWM DUTY CYCLE SWITCH FOR TRUE 0% or 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1129 PERMANENT MAGNET DC MOTOR DRIVE. AN1130 BRUSHLESS DC MOTOR DRIVE WITH ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1182 USING THE ST7 USB LOW-SPEED FIRMWARE PRODUCT OPTIMIZATION AN982 USING CERAMIC RESONATORS WITH THE ST7 AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1070 ST7 CHECKSUM SELFCHECKING CAPABILITY AN1179 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP PRODUCT EVALUATION AN910 ST7 AND ST9 PERFORMANCE BENCHMARKING AN990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1086 ST7 / ST10U435 CAN-do SOLUTIONS FOR CAR MULTIPLEXING AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F8
11.5 TO GET MORE INFORMATION To get the latest information on this product please use the ST web server: http://mcu.st.com/
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12 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision 1.4 Added Figure 99 and Figure 100. Main changes Date Oct-00
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2000 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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